We implemented A/D reading but had issues with the resulting readings

mscovel — Fri, 23 Feb 2018 14:48:36 GMT

We've found that running the K65 A/D at bus clock speed appears to fail in obtaining the full 16 bits of the sample, where for a given constant voltage input, the ADC would report two values with ~240 counts difference, and no values in between. For instance, back to back readings might be 20,400 and 20,640 for a constant voltage.

However, if we divide the A/D clock by 4 or 8 (slow down the A/D clock) that problem is resolved yet we don't see any documentation that tells us we need to do that. We want to find the optimum settings but fear we're not looking in the right place to know for sure what those settings are.

Can you advise about how to achieve the max accuracy at max speed?

Any help you can provide is very much appreciated!

Re: We implemented A/D reading but had issues with the resulting readings

xiangjun_rong — Mon, 26 Feb 2018 05:35:51 GMT

Hi, Mark,

Pls refer to the section 3.6.1.2 16-bit ADC electrical characteristics in data sheet of K65, the fADCK frequency ranges from 1.0MHz to 24MHz for the mode less than or equal to 13 bits mode, or ranges from 2.0MHz to 12Mhz for 16 bits mode.

Regarding the optimum fADCK, we have provided the curve of Typical ADC 16-bit Single-Ended ENOB vs ADC Clock, from the curve, you can see that the ADC16 can give optimum accuacy when the fADCK ranges from 2~6MHz.

I copy the curvbe here:

Hope it can help you

Xiangjun rong

topic We implemented A/D reading but had issues with the resulting readings in Kinetis Microcontrollers

We implemented A/D reading but had issues with the resulting readings

Re: We implemented A/D reading but had issues with the resulting readings