topic K61 HS USB with cache enabled in Kinetis Microcontrollers

K61 HS USB with cache enabled

mrharmonsr — Wed, 17 Jan 2018 16:47:53 GMT

I am using HS USB on a Mk61FN1M0VMJ12 MCU. My code is working when the cache is disabled, but not when it is enabled. Is there some interaction between the cache and HS USB peripheral?

Thanks in advance :smileyhappy:

Re: K61 HS USB with cache enabled

jingpan — Mon, 22 Jan 2018 02:36:19 GMT

Hi Larry,

there isn't a word said that HS USB is conflict with cache. When you use HS USB, you should only close MPU.

Regards

Jing

Re: K61 HS USB with cache enabled

mrharmonsr — Wed, 31 Jan 2018 17:46:27 GMT

I have continued to debug this issue. I've found that in order to use HSUSB with the DDR region cache R8 enabled I needed to move the HSUSB endpoint descriptors, transfer descriptors and buffers to SRAM.

Re: K61 HS USB with cache enabled

mrharmonsr — Wed, 14 Feb 2018 15:58:27 GMT

I am still enable to run the HSUSB with descriptors located in a cached memory region.

However I have improved my situation by using a two DDR regions, one cached and the other non-cached.

I enable caching in region 8 and disable caching in region 7, the aliased address

I am linking the HSUSB descriptors in the cached DDR system section (0x8xxxxxxx) then adjusting the addresses to the aliased, non-cached DDR section (0x7xxxxxxx) by subtracting 0x10000000.

This solution seems to work well.

Re: K61 HS USB with cache enabled

dereksnell — Wed, 14 Feb 2018 16:47:29 GMT

Hi @mrharmonsr ,

I think the K61 block diagram below will help explain what you are seeing. The system cache is used on the two master busses from the Cortex-M4 core, called SYSTEM and CODE bus. Accesses from the other crossbar masters, like the High-Speed USB, do not interact with the cache. When using RAM that is shared between multiple masters, like the USB buffers and descriptors, that RAM should not be cached. The internal SRAM is an ideal location for the USB memory, as it is tightly coupled to the core, so doesn’t benefit from cache, and is accessible by other masters. If you prefer to use external RAM for shared memory, then you can configure a cache region for non-cacheable. Based on the memory map, you can use different cache policies for different cache regions, and divide your DRAM up between cacheable and non-cacheable regions. See Cache Regions table below from the reference manual. For more details on configuring a cache region as non-cacheable, refer to the LMEM_PCCRMR register in the Local Memory Controller chapter of the reference manual. Best regards