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    <title>Kinetis Microcontrollers中的主题 Re: memory question</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/memory-question/m-p/732750#M44804</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The KE series does not implement bit-banding (the description is probably a generic one that is used in all documents).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However it does include a bit-manipulation engine which does more or less the same thing as bit-banding (even with more flexibility, although using different address calculations). Unfortunately it can only access peripherals on the KE parts and not SRAM....&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Mark&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 26 Mar 2018 12:41:19 GMT</pubDate>
    <dc:creator>mjbcswitzerland</dc:creator>
    <dc:date>2018-03-26T12:41:19Z</dc:date>
    <item>
      <title>memory question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/memory-question/m-p/732749#M44803</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear &amp;nbsp;Expert:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;is there a bit-band region of SRAM in KE02(not AIPS)? below is from the KE02 reference manual:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/12531i0A3998B3CDB88862/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;in ke06 refence manual,it is clear description about the SRAM bit_band:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/12414iEE1D8B25732DB3A0/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;thanks for your great support.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 25 Mar 2018 03:43:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/memory-question/m-p/732749#M44803</guid>
      <dc:creator>todtodf</dc:creator>
      <dc:date>2018-03-25T03:43:36Z</dc:date>
    </item>
    <item>
      <title>Re: memory question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/memory-question/m-p/732750#M44804</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The KE series does not implement bit-banding (the description is probably a generic one that is used in all documents).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However it does include a bit-manipulation engine which does more or less the same thing as bit-banding (even with more flexibility, although using different address calculations). Unfortunately it can only access peripherals on the KE parts and not SRAM....&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Mark&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 26 Mar 2018 12:41:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/memory-question/m-p/732750#M44804</guid>
      <dc:creator>mjbcswitzerland</dc:creator>
      <dc:date>2018-03-26T12:41:19Z</dc:date>
    </item>
    <item>
      <title>Re: memory question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/memory-question/m-p/732751#M44805</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Actually all KE families employ Bit Manipulation Engine (BME) techniques to support bit banding.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Mar 2018 08:10:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/memory-question/m-p/732751#M44805</guid>
      <dc:creator>miduo</dc:creator>
      <dc:date>2018-03-27T08:10:27Z</dc:date>
    </item>
    <item>
      <title>Re: memory question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/memory-question/m-p/732752#M44806</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear &amp;nbsp;Expert:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;thanks for your support.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But you can download the AN4838.pdf from &lt;A href="http://www.nxp.com"&gt;www.nxp.com&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The is a description below:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/21127i6AF32AEFD53B16C5/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Mar 2018 04:38:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/memory-question/m-p/732752#M44806</guid>
      <dc:creator>todtodf</dc:creator>
      <dc:date>2018-03-29T04:38:47Z</dc:date>
    </item>
    <item>
      <title>Re: memory question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/memory-question/m-p/732753#M44807</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;KE04 and KE06 are indeed exceptions in that there is really a bit-banding capability in the upper SRAM (I didn't think that any Kinetis Cortex-m0+ parts had it), however it is IS NOT implemented in the KE02.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Mark&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Mar 2018 21:46:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/memory-question/m-p/732753#M44807</guid>
      <dc:creator>mjbcswitzerland</dc:creator>
      <dc:date>2018-03-29T21:46:42Z</dc:date>
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