topic Re: K66 UART behaviour for TC in Kinetis Microcontrollers

K66 UART behaviour for TC

vyacheslavguzhv — Fri, 12 Jan 2018 07:56:32 GMT

Could you please suggest about some not very well documented technical question regarding K66?

Namely we need for K66 using ISO7816 (T=0) UART using 2 stop bits to let IC generate TC interrupt upon first stop bit transmission.

I see that it can be possible in case TC Flag =1 already after first stop bit transmission.

FAE

Re: K66 UART behaviour for TC

miduo — Thu, 18 Jan 2018 08:49:42 GMT

Hello,

Yes, 2 stop bits is supported for ISO7816 T=0 mode. For example to configure UART0 in ISO7816 mode T=0 to support 2 stop bits:

1. enable ISO7816 T=0 mode UART_C1_REG(uartch) |=                            //UART_C1_M_MASK |     /*For 8 data bits only*/                           UART_C1_PT_MASK| //set Odd parity                           UART_C1_PE_MASK; UART_C7816_REG(uartch) = UART_C7816_ISO_7816E_MASK ;2. enable internal pull-up on UART0_TXD and UART0_RXD. if (TERM_PORT == UART0_BASE_PTR)          {             /* Enable the UART0_TXD function on PTD6 */             PORTD_PCR6 = PORT_PCR_MUX(0x3)|PORT_PCR_PE_MASK |PORT_PCR_PS_MASK ; // UART is alt3 function for this pin              /* Enable the UART0_RXD function on PTD7 */             PORTD_PCR7 = PORT_PCR_MUX(0x3)|PORT_PCR_PE_MASK |PORT_PCR_PS_MASK; // UART is alt3 function for this pin         }PS: When baud rate higher than 115200, internal pull-up might be weak, we recommend external pull-ups 4.7K.

Re: K66 UART behaviour for TC

vyacheslavguzhv — Thu, 18 Jan 2018 09:33:56 GMT

hi Li!

thanks for the answer!

I know aboput 2 stop bits support. The question whether the K66 may generate TC interrupt right after first stop bit, but not after the second stop bit?

this is important as in the current solution the answer to the command is sent without any delay.

and it becomes not recognizable once TC comes aftyer second stop bit. I.e. recipient miss first bits of the answer in such case.

Thank you!

Re: K66 UART behaviour for TC

jorge_a_vazquez — Fri, 19 Jan 2018 21:35:22 GMT

Hi Vyacheslav Guzhva

The question whether the K66 may generate TC interrupt right after first stop bit, but not after the second stop bit?

The TC interrupt is set when all the bits has been shifted out from the UART register, so the interrupt is actually triggered when the second stop bit is shifted. So in your device you will see that TC is right after the first stop bit, but it was triggered by the shift of the second bit stop.

Hope this helps.

Best Regards

Jorge Alcala