SIM_SDID Register Read

kaustubhkulkarn — Wed, 28 Feb 2018 11:10:52 GMT

Hello,

I am beginner to the K81 programming. I want to program and read the content of SIM_SDID register (Device unique ID content) using FreeRTOS.

Thus, could you please tell me how can I write a program (start programming) for this or could you please sample code for it

Thank you

Re: SIM_SDID Register Read

danielchen — Mon, 19 Mar 2018 07:52:13 GMT

Hi Kaustubh:

The MCUXpresso SDK provides a peripheral driver for the SIM of MCU-Xpresso SDK devices.

Please refer to fsl_sim.c. Unfortunately, read the SIM_SDID is not implemented. Maybe you can do it by yourself.

/** SIM - Register Layout Typedef */
typedef struct {
__IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
__IO uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
       uint8_t RESERVED_0[4092];
__IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
       uint8_t RESERVED_1[4];
__IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
__IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
       uint8_t RESERVED_2[4];
__IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
       uint8_t RESERVED_3[8];
__I uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
__IO uint32_t SCGC1;                             /**< System Clock Gating Control Register 1, offset: 0x1028 */
__IO uint32_t SCGC2;                             /**< System Clock Gating Control Register 2, offset: 0x102C */
__IO uint32_t SCGC3;                             /**< System Clock Gating Control Register 3, offset: 0x1030 */
__IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
__IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
__IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
__IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
__IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
__IO uint32_t CLKDIV2;                           /**< System Clock Divider Register 2, offset: 0x1048 */
__IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
__I uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
__I uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x1054 */
__I uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
__I uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
__I uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
} SIM_Type;

Regards

Daniel

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