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    <title>topic Re: KV5 TRACE_CLKOUT Divider in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/KV5-TRACE-CLKOUT-Divider/m-p/710771#M43604</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The Trace clock depends on two clock sources - MCGOUTCLK and Core/system in SIM_SOPT2[TRACECLKSEL]. The trace clock divider setup in SIM_CLKDIV4[TRACEFRAC,TRACEDIV]. The TRACE_CLKOUT pin will be at maximum half of the selected clock source.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 26 Sep 2017 08:37:55 GMT</pubDate>
    <dc:creator>miduo</dc:creator>
    <dc:date>2017-09-26T08:37:55Z</dc:date>
    <item>
      <title>KV5 TRACE_CLKOUT Divider</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/KV5-TRACE-CLKOUT-Divider/m-p/710770#M43603</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm using a MKV58 and observing the TRACE_CLKOUT.&amp;nbsp; I found the divider enable in CLKDIV4 disables the output but the divisor appears to have no effect.&amp;nbsp; I only see the fixed divide-by-2 applied to MCGOUTCLK.&amp;nbsp; Are additional configuration steps required?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;SIM-&amp;gt;CLKDIV4 &amp;amp;= ~(SIM_CLKDIV4_TRACEDIV_MASK | SIM_CLKDIV4_TRACEFRAC_MASK);&lt;BR /&gt; SIM-&amp;gt;CLKDIV4 |= (SIM_CLKDIV4_TRACEDIVEN_MASK | SIM_CLKDIV4_TRACEDIV(3U));&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/31426i90561D23E385EA24/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 21 Sep 2017 21:35:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/KV5-TRACE-CLKOUT-Divider/m-p/710770#M43603</guid>
      <dc:creator>ohiogt</dc:creator>
      <dc:date>2017-09-21T21:35:17Z</dc:date>
    </item>
    <item>
      <title>Re: KV5 TRACE_CLKOUT Divider</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/KV5-TRACE-CLKOUT-Divider/m-p/710771#M43604</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The Trace clock depends on two clock sources - MCGOUTCLK and Core/system in SIM_SOPT2[TRACECLKSEL]. The trace clock divider setup in SIM_CLKDIV4[TRACEFRAC,TRACEDIV]. The TRACE_CLKOUT pin will be at maximum half of the selected clock source.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 Sep 2017 08:37:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/KV5-TRACE-CLKOUT-Divider/m-p/710771#M43604</guid>
      <dc:creator>miduo</dc:creator>
      <dc:date>2017-09-26T08:37:55Z</dc:date>
    </item>
    <item>
      <title>Re: KV5 TRACE_CLKOUT Divider</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/KV5-TRACE-CLKOUT-Divider/m-p/710772#M43605</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Fang,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I understand the basic operation, my issue is that the divisor and frac settings appear to have no effect on the clock output.&amp;nbsp; Do you have any information on this?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Shawn&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 Sep 2017 21:07:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/KV5-TRACE-CLKOUT-Divider/m-p/710772#M43605</guid>
      <dc:creator>ohiogt</dc:creator>
      <dc:date>2017-09-26T21:07:59Z</dc:date>
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