topic [SPI] MOSI is changed from level '0' to level '1' before the falling edge happens in Kinetis Microcontrollers

[SPI] MOSI is changed from level '0' to level '1' before the falling edge happens

mohammedaboelna — Thu, 17 Aug 2017 12:09:21 GMT

Greetings,

I am using KIT TRK-KEAZN64

I am configuring SPI peripheral as below; SPI0_C1 = BIT_SPIC0_SPE | BIT_SPIC0_MSTR | BIT_SPIC0_CPHA | BIT_SPIC0_CPOL; SPE = 1

=> Enable SPI system, MSTR = 1

=> Set SPI as master device, CPHA = 1

=> First edge at start of first data transfer cycle, CPOL = 1

=> SPI clock as active low (idle high).

So I am expecting MOSI to be changed at every falling edge of the clock. However, I had strange behavior which is in case of MOSI change from level '0' to level '1', this change occurs vefore the falling edge of clock happens. while it is working good when MOSI changes from level '1' to level '0'. This is illustrated more in the attached screenshots.

Re: [SPI] MOSI is changed from level '0' to level '1' before the falling edge happens

xiangjun_rong — Tue, 22 Aug 2017 03:40:00 GMT

Dear Mohammed,

If you configure the SPI module of KEA processor in master mode and CPHA=CPOL=1, from theory, the falling edge of SPI clock signal SPSCK will trigger the MOSI signal toggle. Regarding your obvervation that the falling edge of SPCLK lags behind the MOSI rising edge, because you use logic analyzer, cable length, pin capacitive difference may leads to the issue.
how about using high frequency oscilloscope to test the signals while you connect the proble to the KEA chip pins as close as possible and remove the capactive load?

Hope it can help you

xiangjun Rong