MK12DN512VLK5 - Contradictory flash clock divider requirements

tomscott — Mon, 11 Sep 2017 16:23:57 GMT

Reference Manual: K12P80M50SF4RM, Rev 4, Feb 2013

Page 134, Section 5.5: "The flash clock frequency must be programmed to 25 MHz or less and an integer
divide of the bus clock."

Page 233, Section 12.2.11 - System Clock Divider Register 1 (SIM_CLKDIV1):

OUTDIV4 - "The flash clock frequency must be an integer divide of the system clock frequency."

I would like to set the clocks up as follows:

48 MHz core/system

8 MHz bus

24 MHz flash

I can do this following the requirement on page 233, but not the requirement on page 134.

Which requirement is correct?

Re: MK12DN512VLK5 - Contradictory flash clock divider requirements

jorge_a_vazquez — Tue, 12 Sep 2017 00:41:21 GMT

Hi Tom scott

Sorry for the misunderstanding description in the reference manual, the note in the page 134 should be like

The flash clock frequency must be programmed to 25 MHz or less, less than or equal to the bus clock, and an integer divide of the core clock.

So you cannot have

48 MHz core/system

8 MHz bus

24 MHz flash

Hope this information could help you.
Have a great day,
Jorge Alcala

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Kinetis MicrocontrollersのトピックMK12DN512VLK5 - Contradictory flash clock divider requirements

MK12DN512VLK5 - Contradictory flash clock divider requirements

Re: MK12DN512VLK5 - Contradictory flash clock divider requirements