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    <title>topic MK66 custom board, using USB1, no PLL lock in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK66-custom-board-using-USB1-no-PLL-lock/m-p/688917#M42389</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm developing an application which uses the High speed USB in device mode from the Kinetis 66. I based my code on the CDC + MSC lite example code from the MCUXpresso SDK.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I got it to build in our custom environment (after removing the MSC part, I don't need it). But the processor gets stuck in the APPInit, when it is checking for the USBPHY PLL to lock (function bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I've found several topics covering the issue, and walked through them:&lt;/P&gt;&lt;P&gt;- we use the xtal mode, not extosc, so no ERRATA_ID_9712 dependency (&lt;SPAN class="" style="max-width: 786px;"&gt;&lt;A class="jive-link-thread-small" data-containerid="2019" data-containertype="14" data-objectid="434911" data-objecttype="1" href="https://community.nxp.com/thread/434911"&gt;https://community.nxp.com/message/852272&lt;/A&gt;&lt;/SPAN&gt;)&lt;/P&gt;&lt;P&gt;- correct xtal (16 MHz)&lt;/P&gt;&lt;P&gt;- I have a correct voltage on USB VREG pin (3v3) delivered from VREG_IN1 and VREG_IN0&lt;/P&gt;&lt;P&gt;- all assert() statements in the beginning of the function checked out correctly&lt;/P&gt;&lt;P&gt;-- 32k is running&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I didn't check any runmode in previous init routines, but can they interfere with the settings introduced in this function, stopping the PLL to lock?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please advice.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 23 May 2017 14:16:01 GMT</pubDate>
    <dc:creator>H_Grobben</dc:creator>
    <dc:date>2017-05-23T14:16:01Z</dc:date>
    <item>
      <title>MK66 custom board, using USB1, no PLL lock</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK66-custom-board-using-USB1-no-PLL-lock/m-p/688917#M42389</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm developing an application which uses the High speed USB in device mode from the Kinetis 66. I based my code on the CDC + MSC lite example code from the MCUXpresso SDK.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I got it to build in our custom environment (after removing the MSC part, I don't need it). But the processor gets stuck in the APPInit, when it is checking for the USBPHY PLL to lock (function bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I've found several topics covering the issue, and walked through them:&lt;/P&gt;&lt;P&gt;- we use the xtal mode, not extosc, so no ERRATA_ID_9712 dependency (&lt;SPAN class="" style="max-width: 786px;"&gt;&lt;A class="jive-link-thread-small" data-containerid="2019" data-containertype="14" data-objectid="434911" data-objecttype="1" href="https://community.nxp.com/thread/434911"&gt;https://community.nxp.com/message/852272&lt;/A&gt;&lt;/SPAN&gt;)&lt;/P&gt;&lt;P&gt;- correct xtal (16 MHz)&lt;/P&gt;&lt;P&gt;- I have a correct voltage on USB VREG pin (3v3) delivered from VREG_IN1 and VREG_IN0&lt;/P&gt;&lt;P&gt;- all assert() statements in the beginning of the function checked out correctly&lt;/P&gt;&lt;P&gt;-- 32k is running&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I didn't check any runmode in previous init routines, but can they interfere with the settings introduced in this function, stopping the PLL to lock?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please advice.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 23 May 2017 14:16:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK66-custom-board-using-USB1-no-PLL-lock/m-p/688917#M42389</guid>
      <dc:creator>H_Grobben</dc:creator>
      <dc:date>2017-05-23T14:16:01Z</dc:date>
    </item>
    <item>
      <title>Re: MK66 custom board, using USB1, no PLL lock</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK66-custom-board-using-USB1-no-PLL-lock/m-p/688918#M42390</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I found that it is important to have the USB VREG for the K65's PLL to lock &lt;EM&gt;but not the K66&lt;/EM&gt;. The FRDM-K66F board doesn't have this connected and I found that the PLL &lt;EM&gt;always locks&lt;/EM&gt;, even without VREG.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Do a comparison with the K66 targets in the uTasker project (it supports HS CDC, MSB, HID, Audio composite devices on various K65/K66 boards, including FRDM-K66F and Teensy 3.6)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Web:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FuTasker%2FuTasker-Kinetis" rel="nofollow" target="_blank"&gt;https://github.com/uTasker/uTasker-Kinetis&lt;/A&gt;&lt;BR /&gt;&lt;SPAN&gt;HTTPS:&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FuTasker%2FuTasker-Kinetis.git" rel="nofollow" target="_blank"&gt;https://github.com/uTasker/uTasker-Kinetis.git&lt;/A&gt;&lt;BR /&gt;&lt;SPAN&gt;SSH:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;A class="jive-link-email-small" href="mailto:git@github.com"&gt;git@github.com&lt;/A&gt;&lt;SPAN&gt;:uTasker/uTasker-Kinetis.git&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Mark&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 23 May 2017 16:56:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK66-custom-board-using-USB1-no-PLL-lock/m-p/688918#M42390</guid>
      <dc:creator>mjbcswitzerland</dc:creator>
      <dc:date>2017-05-23T16:56:11Z</dc:date>
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