Kinetis MicrocontrollersのトピックRe: MKV10Z64 - VLPS - high current draw https://community.nxp.com/t5/Kinetis-Microcontrollers/MKV10Z64-VLPS-high-current-draw/m-p/675908#M41567 <HTML><HEAD></HEAD><BODY><P>Test the same project and same MCU with two FRDM-KV10Z boards, get different current in VLPS. <BR />Compare hardware of the FRDM-KV10Z, find the J12 will lead the current leakage. After cut the trace of J12 at bottom side, the current in VLPS of my FRDM-KV10Z board down to about 40μA.</P><P><span class="lia-inline-image-display-wrapper" image-alt="Isolation UART SWD_DIO.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/19929i9C096899A3D79341/image-size/large?v=v2&amp;px=999" role="button" title="Isolation UART SWD_DIO.png" alt="Isolation UART SWD_DIO.png" /></span></P><P></P><P>Test the same project and same MCU with two FRDM-KV10Z boards but using different firmware applications for onboard OpenSDA, get different current in VLPS. <BR />Compare firmware application of onboard OpenSDA, find different J-Link firmware will set different voltage to UART1_TX_TGTMCU_R. When use newest Board-Specific Firmwares'19_OpenSDA_FRDM-KV10Z.bin', the PTB17/UART0_TX current leakage occurs.</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>Conclusion:<BR />We think it meet the 'Internal pull-up/down case' in <A href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fprocessors.wiki.ti.com%2Findex.php%2FOptimizing_IO_Power_Consumption" rel="nofollow" target="_blank">Optimizing IO Power Consumption</A>. Customer should avoid this.</P><P><span class="lia-inline-image-display-wrapper" image-alt="Fig3_internalpullupdowncell.JPG"><img src="https://community.nxp.com/t5/image/serverpage/image-id/19968iF8D0E50B3F3D15F8/image-size/large?v=v2&amp;px=999" role="button" title="Fig3_internalpullupdowncell.JPG" alt="Fig3_internalpullupdowncell.JPG" /></span></P><P></P><P>Best Regards,</P><P>Robin</P><P style="min- padding: 0px;">&nbsp;</P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Thu, 08 Jun 2017 00:53:06 GMT Robin_Shen 2017-06-08T00:53:06Z MKV10Z64 - VLPS - high current draw https://community.nxp.com/t5/Kinetis-Microcontrollers/MKV10Z64-VLPS-high-current-draw/m-p/675907#M41566 <HTML><HEAD></HEAD><BODY><P>Greetings. I am using the above MCU in a device I am developing. Sleep current in VLPS is ~380uA (confirmed that this is the draw of the MCU alone). Per the datasheet, it should be much much lower. I am using the functions per SDK2.2 to enter VLPS, I am seeing a drop from run time draw (~2mA) to this sleep current draw, so I know that the MCU is entering a lower power state, but I cannot achieve the numbers I expect. All un-used pins are pulled low using internal pull downs and driven low (excluding the JTAG lines - although I suppose I could add them to the list too). Any ideas about what else I should check? Is something defaulted to on (via SDK2.2 or otherwise) that I should be disabling? I believe the core clock is disabled in VLPS so no value in dropping clock speed when sleeping, correct?</P><P></P><P>Any help is appreciated!</P><P></P><P>-Chris</P></BODY></HTML> Thu, 11 May 2017 15:07:07 GMT https://community.nxp.com/t5/Kinetis-Microcontrollers/MKV10Z64-VLPS-high-current-draw/m-p/675907#M41566 chrisphelan 2017-05-11T15:07:07Z Re: MKV10Z64 - VLPS - high current draw https://community.nxp.com/t5/Kinetis-Microcontrollers/MKV10Z64-VLPS-high-current-draw/m-p/675908#M41567 <HTML><HEAD></HEAD><BODY><P>Test the same project and same MCU with two FRDM-KV10Z boards, get different current in VLPS. <BR />Compare hardware of the FRDM-KV10Z, find the J12 will lead the current leakage. After cut the trace of J12 at bottom side, the current in VLPS of my FRDM-KV10Z board down to about 40μA.</P><P><span class="lia-inline-image-display-wrapper" image-alt="Isolation UART SWD_DIO.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/19929i9C096899A3D79341/image-size/large?v=v2&amp;px=999" role="button" title="Isolation UART SWD_DIO.png" alt="Isolation UART SWD_DIO.png" /></span></P><P></P><P>Test the same project and same MCU with two FRDM-KV10Z boards but using different firmware applications for onboard OpenSDA, get different current in VLPS. <BR />Compare firmware application of onboard OpenSDA, find different J-Link firmware will set different voltage to UART1_TX_TGTMCU_R. When use newest Board-Specific Firmwares'19_OpenSDA_FRDM-KV10Z.bin', the PTB17/UART0_TX current leakage occurs.</P><P style="min-height: 8pt; padding: 0px;">&nbsp;</P><P>Conclusion:<BR />We think it meet the 'Internal pull-up/down case' in <A href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fprocessors.wiki.ti.com%2Findex.php%2FOptimizing_IO_Power_Consumption" rel="nofollow" target="_blank">Optimizing IO Power Consumption</A>. Customer should avoid this.</P><P><span class="lia-inline-image-display-wrapper" image-alt="Fig3_internalpullupdowncell.JPG"><img src="https://community.nxp.com/t5/image/serverpage/image-id/19968iF8D0E50B3F3D15F8/image-size/large?v=v2&amp;px=999" role="button" title="Fig3_internalpullupdowncell.JPG" alt="Fig3_internalpullupdowncell.JPG" /></span></P><P></P><P>Best Regards,</P><P>Robin</P><P style="min- padding: 0px;">&nbsp;</P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Thu, 08 Jun 2017 00:53:06 GMT https://community.nxp.com/t5/Kinetis-Microcontrollers/MKV10Z64-VLPS-high-current-draw/m-p/675908#M41567 Robin_Shen 2017-06-08T00:53:06Z