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    <title>topic Re: What are the main differences between K65 and K66? in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/What-are-the-main-differences-between-K65-and-K66/m-p/660346#M40527</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Xiangjun,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Here are the reasons why i think K66 only supports 16 bit wide SDRAM blocks and its likely documentation error on NXP's account.&lt;/P&gt;&lt;P&gt;1. &amp;nbsp;If you look at&amp;nbsp;K66P144M180SF5V2.pdf, the hardware manual, look at Figure 15, it only shows data bits from 31-16.&lt;/P&gt;&lt;P&gt;2. &amp;nbsp;If you go to section 5 of the same doc, the pinout section and multiplexing assignments, you can only find 16 bits for the SDRAM data lines.&lt;/P&gt;&lt;P&gt;3. &amp;nbsp;Also see this thread. &amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/thread/388002"&gt;https://community.nxp.com/thread/388002&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I just wanted confirmation from someone from NXP. &amp;nbsp;Looks like documentation still hasn't been updated.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 15 Dec 2016 18:49:12 GMT</pubDate>
    <dc:creator>eico</dc:creator>
    <dc:date>2016-12-15T18:49:12Z</dc:date>
    <item>
      <title>What are the main differences between K65 and K66?</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/What-are-the-main-differences-between-K65-and-K66/m-p/660344#M40525</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;When compared to the K65, the K66 is slightly larger, has no anti-tamper pins, but has the same performance as the K65 w/ the CAU, power consumption, etc. &amp;nbsp;One major difference was also that the K66 only supports 16-bit SDRAM interface vs. the K65's 32-bit SDRAM interface. &amp;nbsp;Are these statements accurate (especially the SDRAM interface part)?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Dec 2016 18:37:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/What-are-the-main-differences-between-K65-and-K66/m-p/660344#M40525</guid>
      <dc:creator>eico</dc:creator>
      <dc:date>2016-12-08T18:37:35Z</dc:date>
    </item>
    <item>
      <title>Re: What are the main differences between K65 and K66?</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/What-are-the-main-differences-between-K65-and-K66/m-p/660345#M40526</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, &lt;/P&gt;&lt;P&gt;your statements are not accurate, the SDRAM controller of both K66 and K65 supports 8/16/32 bits SDRAM.&lt;/P&gt;&lt;P&gt;I copy the part from UM of K66:&lt;/P&gt;&lt;P&gt;35.3 Overview&lt;BR /&gt;The synchronous DRAM controller module provides glueless integration of SDRAM.&lt;BR /&gt;The key features of the DRAM controller include the following:&lt;BR /&gt;• Support for two independent blocks of SDRAM&lt;BR /&gt;• Interface to standard SDRAM components&lt;BR /&gt;• Programmable SRAS, SCAS, and refresh timing&lt;BR /&gt;• Support for 8-, 16-, and 32-bit wide SDRAM blocks&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope it can help you&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Xiangjun Rong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Dec 2016 06:52:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/What-are-the-main-differences-between-K65-and-K66/m-p/660345#M40526</guid>
      <dc:creator>xiangjun_rong</dc:creator>
      <dc:date>2016-12-09T06:52:38Z</dc:date>
    </item>
    <item>
      <title>Re: What are the main differences between K65 and K66?</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/What-are-the-main-differences-between-K65-and-K66/m-p/660346#M40527</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Xiangjun,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Here are the reasons why i think K66 only supports 16 bit wide SDRAM blocks and its likely documentation error on NXP's account.&lt;/P&gt;&lt;P&gt;1. &amp;nbsp;If you look at&amp;nbsp;K66P144M180SF5V2.pdf, the hardware manual, look at Figure 15, it only shows data bits from 31-16.&lt;/P&gt;&lt;P&gt;2. &amp;nbsp;If you go to section 5 of the same doc, the pinout section and multiplexing assignments, you can only find 16 bits for the SDRAM data lines.&lt;/P&gt;&lt;P&gt;3. &amp;nbsp;Also see this thread. &amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/thread/388002"&gt;https://community.nxp.com/thread/388002&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I just wanted confirmation from someone from NXP. &amp;nbsp;Looks like documentation still hasn't been updated.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 15 Dec 2016 18:49:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/What-are-the-main-differences-between-K65-and-K66/m-p/660346#M40527</guid>
      <dc:creator>eico</dc:creator>
      <dc:date>2016-12-15T18:49:12Z</dc:date>
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