Kinetis MicrocontrollersのトピックRe: Embedded Trace Macrocell (ETM) PCB Routing Tips https://community.nxp.com/t5/Kinetis-Microcontrollers/Embedded-Trace-Macrocell-ETM-PCB-Routing-Tips/m-p/658164#M40355 <HTML><HEAD></HEAD><BODY><P>The best reference I've found for this is the Segger J-Link/J-Trace manual. </P><P></P><P><A class="link-titled" href="https://www.segger.com/products/debug-probes/j-link/" title="https://www.segger.com/products/debug-probes/j-link/">J-Link Debug Probes | SEGGER - The Embedded Experts</A>&nbsp;</P><P></P><P>Chapter 17 (as of this post) called "Designing the target board for trace"</P></BODY></HTML> Thu, 15 Feb 2018 17:06:47 GMT pgvoorhees 2018-02-15T17:06:47Z Embedded Trace Macrocell (ETM) PCB Routing Tips https://community.nxp.com/t5/Kinetis-Microcontrollers/Embedded-Trace-Macrocell-ETM-PCB-Routing-Tips/m-p/658163#M40354 <HTML><HEAD></HEAD><BODY><P>Hello Community, </P><P>We are planning on using ETM to aid in debugging but have found very few routing guidelines for the TRACE_D[0:3] and TRACE_CLK nets.</P><P></P><P>On the K22FX512, using a 120MHz core speed, What is:</P><UL><LI>The clock speed of the TRACE nets? Datasheet says the interface is limited to 50MHz but offers no guidance for determining the speed.</LI><LI>Is any particular characteristic impedance for the traces necessary?</LI><LI>Do the lines need to be length-matched?</LI></UL><P></P><P>Design guild-lines seem to be largely unavailable and the Kinetis datasheets are light on details for this particular functionality. Any help is appreciated. Thanks!</P></BODY></HTML> Thu, 16 Mar 2017 13:26:22 GMT https://community.nxp.com/t5/Kinetis-Microcontrollers/Embedded-Trace-Macrocell-ETM-PCB-Routing-Tips/m-p/658163#M40354 pgvoorhees 2017-03-16T13:26:22Z Re: Embedded Trace Macrocell (ETM) PCB Routing Tips https://community.nxp.com/t5/Kinetis-Microcontrollers/Embedded-Trace-Macrocell-ETM-PCB-Routing-Tips/m-p/658164#M40355 <HTML><HEAD></HEAD><BODY><P>The best reference I've found for this is the Segger J-Link/J-Trace manual. </P><P></P><P><A class="link-titled" href="https://www.segger.com/products/debug-probes/j-link/" title="https://www.segger.com/products/debug-probes/j-link/">J-Link Debug Probes | SEGGER - The Embedded Experts</A>&nbsp;</P><P></P><P>Chapter 17 (as of this post) called "Designing the target board for trace"</P></BODY></HTML> Thu, 15 Feb 2018 17:06:47 GMT https://community.nxp.com/t5/Kinetis-Microcontrollers/Embedded-Trace-Macrocell-ETM-PCB-Routing-Tips/m-p/658164#M40355 pgvoorhees 2018-02-15T17:06:47Z