Kinetis MicrocontrollersのトピックK65 UART FIFO error

K65 UART FIFO error

charlesklibbe — Tue, 21 Feb 2017 11:48:39 GMT

We need to use UART1 at 3.6864Mbps with the FIFO and although it works there is a hardware failure. At random times the RDRF flag in S1 is set but when you read the RCFIFO it is zero causing an endless interrupt loop.

From the interrupt handler:

void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle)
{

...

/* Receive data register full */
if ((UART_S1_RDRF_MASK & base->S1) && (UART_C2_RIE_MASK & base->C2))
{
/* Get the size that can be stored into buffer for this interrupt. */
#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
count = base->RCFIFO;
#else
count = 1;
#endif

if (count == 0) {
__ASM("NOP"); // Breakpoint
}

/* If handle->rxDataSize is not 0, first save data to handle->rxData. */
while ((count) && (handle->rxDataSize))
{

...

The data register is not read as the count is zero. If I try to resolve the issue by reading the data register the RXUF flag in the SFIFO register gets set indicating that there was no data in the FIFO.

The problem is more pronounced if the baud rate division is below 3, 180MHZ / 16 / 3801600 = 2.959, as then it fails within a few bytes. If using a lower baud rate of say 921600 then there is no problem.

The FIFO water mark is set to 2 and I'm using 8,n,1.

Can anyone shed some light on the problem please?

Regards,

Charles

Re: K65 UART FIFO error

viniciuskawakam — Thu, 07 Dec 2017 16:57:14 GMT

I'm having the same problem, I work with the K22F processor and whem I read the RCFIFO it is zero causing infinite lupping.

Anyone have any idea what the problem might be?

Re: K65 UART FIFO error

ETCTim — Wed, 12 Sep 2018 14:47:49 GMT

Same problem. Was there ever a fix for it?

Thanks,

TIm

Re: K65 UART FIFO error

mjbcswitzerland — Wed, 12 Sep 2018 20:12:00 GMT

Is it sure that no overruns are involved? In the case of an overrun there may be a reception interrupt left which needs the data register to be read (even when nothing in it) to clear it.

The interrupt handler looks also suspect - I think it is safer to unconditionally read the data register and then check whether there is still data (and repeat if necessary) rater than base the operation on the Fifo status on entry.

Using DMA should also avoid such issues.

Regards

Mark