topic Re: CMSIS DRIVERS in Kinetis Microcontrollers

CMSIS DRIVERS

maheshwarreddy — Tue, 27 Sep 2016 04:52:14 GMT

hi,

I wants to use the CMSIS,RTX drivers for the k66 controller in KEIL IDE how can I use these.,

Re: CMSIS DRIVERS

xiangjun_rong — Wed, 28 Sep 2016 02:24:37 GMT

Hi, Maheshwar,

Pls go to the website, download SDK2.0 package for K66.

http://www.nxp.com/ksdk

click SDK Builder, select K66, SDK2.0 and Keil, unzip the package.

You will find the directory for CMSIS.

C:\Freescale\SDK2.0_TWR-K65\CMSIS

In the directory, it include the library and source code for FIR/IIR/FFT/sin/cos...

Hope it can help you.

Xiangjun Rong

Re: CMSIS DRIVERS

maheshwarreddy — Wed, 28 Sep 2016 08:47:38 GMT

hi,

it is not getting downloaded can u attach that full file.

Re: CMSIS DRIVERS

maheshwarreddy — Wed, 28 Sep 2016 09:28:10 GMT

hi,

i found the file ,also how can i use the rtx drivers for the k66, the CMSIS are same as the stack

Re: CMSIS DRIVERS

xiangjun_rong — Wed, 28 Sep 2016 09:38:06 GMT

Hi,

what do you mean "RTX" driver?

Xiangjun Rong

Re: CMSIS DRIVERS

maheshwarreddy — Wed, 28 Sep 2016 09:41:31 GMT

hi ,

i to don't know when iam using keil5 it asks for the RTX drivers (while creating a project ). if you know how to use the CMSIS and RTX drivers in the keil5 can you send a document

Re: CMSIS DRIVERS

xiangjun_rong — Thu, 29 Sep 2016 03:00:21 GMT

Hi, Maheshwar,

I am not familiar with keil tools and RTX driver, but I have asked another engineer, we do not support the RTX driver for peripherals in Keil. But NXP has KDS tools, and SDK with FreeRTOS for Kinetis.

Xiangjun Rong

Re: CMSIS DRIVERS

maheshwarreddy — Thu, 29 Sep 2016 05:55:14 GMT

hi ,

Now iam using the sdk2.0 for the udp echo application (in the hardware we are applying the clock at EXTAL(pin.n0 72 with 50MHz) as reference clock )and iam not applying any other clock now I wants to operate the processor at 180 MHz speed and the Ethernet application is in RMII mode

what are the changes I needs to made .

Re: CMSIS DRIVERS

xiangjun_rong — Thu, 29 Sep 2016 09:06:34 GMT

I suppose you have downloaded and installed SDK2.0 based on K66.

Pls refer to the example:

C:\Freescale\SDK2.0_TWR-K65\boards\twrk65f180m\demo_apps\lwip\lwip_tcpecho\freertos

You can see the code in clcok_config.c

assume you use 50Mhz clock source hooked to EXTAL0 pin rather than a 16mhz crystal hooked on EXTAL0/XTAL0 pins as TWR-K65 board, you can modify it as:

Original:

/* Configuration for HSRUN mode. Core clock = 180MHz. */
const clock_config_t g_defaultClockConfigHsrun = {
    .mcgConfig =
        {
            .mcgMode = kMCG_ModePEE,             /* Work in PEE mode. */
            .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
            .ircs = kMCG_IrcSlow,                /* Select IRC32k. */
            .fcrdiv = 0U,                        /* FCRDIV is 0. */

            .frdiv = 4U,
            .drs = kMCG_DrsLow,         /* Low frequency range */
            .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
            .oscsel = kMCG_OscselOsc,   /* Select OSC */

            .pll0Config =
                {
                    .enableMode = 0U, .prdiv = 0x01U, .vdiv = 0x1DU,
                },
            .pllcs = kMCG_PllClkSelPll0,
        },
    .simConfig =
        {
            .pllFllSel = 1U,        /* PLLFLLSEL select PLL. */
            .pllFllDiv = 0U,        /* PLLFLLSEL clock divider divisor */
            .pllFllFrac = 0U,       /* PLLFLLSEL clock divider fraction */
            .er32kSrc = 2U,         /* ERCLK32K selection, use RTC. */
            .clkdiv1 = 0x02260000U, /* SIM_CLKDIV1. */
        },
    .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
                  .capLoad = 0,
                  .workMode = kOSC_ModeOscLowPower,
                  .oscerConfig =
                      {
                          .enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
                          .erclkDiv = 0U,
#endif
                      }},
    .coreClock = 180000000U, /* Core clock frequency */
};

Modification by Rong:

            .pll0Config =
                {
                    .enableMode = 0U, .prdiv = 0x04U, .vdiv = 0x14U,   ///Modified by Rong:{50MHz/(4+1)} * 36, the VCO will output 360mhz, MCGPLLCLK is //360Mhz/2=180MHz
                },
            .pllcs = kMCG_PllClkSelPll0,
        },
    .simConfig =
        {
            .pllFllSel = 1U,        /* PLLFLLSEL select PLL. */
            .pllFllDiv = 0U,        /* PLLFLLSEL clock divider divisor */
            .pllFllFrac = 0U,       /* PLLFLLSEL clock divider fraction */
            .er32kSrc = 2U,         /* ERCLK32K selection, use RTC. */
            .clkdiv1 = 0x02260000U, /* SIM_CLKDIV1. */
        },
    .oscConfig = {.freq = 50000000; //50mHz //BOARD_XTAL0_CLK_HZ, Modified by Rong
                  .capLoad = 0,
                  .workMode = kOSC_ModeOscLowPower,
                  .oscerConfig =
                      {
                          .enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
                          .erclkDiv = 0U,
#endif
                      }},
    .coreClock = 180000000U, /* Core clock frequency */
};

I do not test it, you can have a try.

Hope it can help you.

Xiangjun Rong

Re: CMSIS DRIVERS

maheshwarreddy — Thu, 29 Sep 2016 17:57:29 GMT

hi ,

Thank you,is it possible to reduce the size of the code size , i need more memory for the other application development

Re: CMSIS DRIVERS

xiangjun_rong — Fri, 30 Sep 2016 01:50:31 GMT

Hi,

I am afraid that it is difficult to reduce code size, because the SDK uses predefined structure.

Xiangjun Rong

Re: CMSIS DRIVERS

maheshwarreddy — Fri, 30 Sep 2016 11:51:04 GMT

hi,

how to manage that memory issue . and if I wants to use both usb and Ethernet in the same project what are the files I needs to include

Re: CMSIS DRIVERS

maheshwarreddy — Sat, 01 Oct 2016 10:40:02 GMT

hi, how to send and receive the udp frame by using the udp echo . how the frame formate is organised .

Re: CMSIS DRIVERS

maheshwarreddy — Mon, 03 Oct 2016 17:09:02 GMT

hi, iam using UDP echo but the data is not coming out of the processor