Kinetis Microcontrollers中的主题 Re: KL16 I2S Master Mode - Generating Clock Signals

KL16 I2S Master Mode - Generating Clock Signals

lancebantoto — Wed, 05 Apr 2017 11:43:29 GMT

Hello,

I am using the MKL16Z256VMP4 as an I2S master. Can it generate the following synchronized clock frequencies?

SAI_TX_BCLK 3.072 MHz
SAI_TX_FS 48 kHz
I2S_MCLK 6.144/12.288/24.756 MHz

I have read through the KL16 Sub-Family Reference Manual Rev 3.2 but am unsure of how SAI_TX_FS is configured.

Thanks in advance!

Lance

Re: KL16 I2S Master Mode - Generating Clock Signals

Hui_Ma — Thu, 06 Apr 2017 04:49:44 GMT

Hi Lance,

Due to the requirement, the bit clock is 3.072MHz with Transmitter frame sync frequency 48KHz.
3.072MHz/48KHz = 64
So, the data frame need contain 2 words, each word contains 32 bits.
I2S0_TCR4 register [FRSZ] = 0b1; [SYWD] = 0b11111;
I2S0_TCR5 register [WNW] = 0b11111; [W0W] = 0b11111;

Wish it helps.

Have a great day,
Ma Hui

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Re: KL16 I2S Master Mode - Generating Clock Signals

lancebantoto — Thu, 06 Apr 2017 12:54:23 GMT

Thank you.

Why does the data frame need to contain 2 words?

Can this frame sync frequency be used as a clock output when no data is being transmitted or received? This application just needs these three synchronized frequencies to be output.

Lance

Re: KL16 I2S Master Mode - Generating Clock Signals

Hui_Ma — Mon, 10 Apr 2017 09:28:30 GMT

Hi Lance,

I am checking with this issue. I will let you know soon.

Thank you for the patience.

Have a great day,
Ma Hui

Re: KL16 I2S Master Mode - Generating Clock Signals

lancebantoto — Mon, 10 Apr 2017 14:12:31 GMT

Thank you!

Re: KL16 I2S Master Mode - Generating Clock Signals

Hui_Ma — Tue, 11 Apr 2017 10:13:13 GMT

Hi Lance,

Sorry for the later reply.

The frame sync clock will based on SAI Transmit Configuration 4 Register (I2Sx_TCR4) [SYWD] bit about active level bit clock number. When, set data frame with 2 words, each word 32 bit, the total frame sync signal bit clock is (32bit active level + 32bit inactive level, total 64bit ).

When customer need just three clock signals output, it need to continue to transmit the data output(whatever the data value). So, there need to use DMA engineer to move data to SAI Transmit Data Register (I2Sx_TDRn) continuously.

We are curious why customer consider this kind of application of SAI module.

We also suggest customer to use PTC3(CLKOUT) pin to output the I2S_MCLK clock(OSCERCLK) ;

using two TPM modules to output SAI_TX_BCLK clock and SAI_TX_FS clock.

Wish it helps.

Have a great day,
Ma Hui

Re: KL16 I2S Master Mode - Generating Clock Signals

lancebantoto — Tue, 11 Apr 2017 14:38:01 GMT

Hi Ma Hui,

I am trying to use the MCU as the I2S master as shown in the diagram above. Hope it helps.