topic Re: KL46Z PLL in Kinetis Microcontrollers

KL46Z PLL

briceagbebe-cos — Sun, 06 Nov 2016 14:50:17 GMT

Hello,

I try to configure the PLL of the KL46Z FRDM board with an 8MHz external oscillator. I followed every step from the datasheet in order to switch the MCG from FEI to PEE mode, but nothing happens. I'm expecting to light up two LEDs every one second.

#include "derivative.h" 

#define CLKSTS_MASK 0x08
#define CLKST_MASK  0x0C

static void BootClockRUN();

void setup(void)
{
        

            BootClockRUN();

         SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK; /*System Clock Gating Control Register 5 (SIM_SCGC5)*/
         SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK; /*Enable clock for PORT E setting bit field PORTE*/
                                            /*Also enable clock for PORT D setting bit field PORTE*/
          
         
         PORTE_PCR29 = PORT_PCR_MUX(1);      /*Pin Control Register n (PORTx_PCRn)*/
         PORTD_PCR5 = PORT_PCR_MUX(1);       /*Select GPIO as pin functionality on multiplexor*/
                                        /*setting field MUX=001, do this for each bit on each PORT*/
         
         GPIOE_PDDR |= (1 << 29);            /*Port Data Direction Register (GPIOx_PDDR)*/
         GPIOD_PDDR |= (1 << 5);          /*Set GPIO direction set bit corresponding bit on the direction*/
                        
                        
        
   unsigned long time = 48000000;
   unsigned long counter;
      while(1)
       {
             GPIOE_PTOR |= (1<<29);
             for(counter = 0; counter < time; counter++){}
             GPIOD_PTOR |= (1<<5);
          }
}


void BootClockRUN()
{
        MCG_C2 = 0x2C;
        MCG_C1 = 0x90;

        while(!(MCG_S & (1<<1)));
        
        while((MCG_S & (1<<4)));

        while((MCG_S & CLKSTS_MASK) != CLKSTS_MASK);

        MCG_C5 = 0x01;

        MCG_C6 = 0x40;

        while(!(MCG_S & (1<<5)));
        
        while(!(MCG_S & (1<<6)));

        MCG_C1 = 0x10;

       while((MCG_S & CLKST_MASK) != CLKST_MASK); 
}‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

Could someone tells me what the problem is?

Thank you,

Best Regards,

Re: KL46Z PLL

mjbcswitzerland — Mon, 07 Nov 2016 11:19:20 GMT

This is code to initialise to run a KL46 at 48MHz (24MHz bus and flash) from an 8MHz crystal [the hex values are noted in brackets for simple comparison]:

MCG_C2 = (MCG_C2_RANGE_1M_8M | MCG_C2_GAIN_MODE | MCG_C2_EREFS | MCG_C2_LOCRE0); // select crystal oscillator and select a suitable range [0x9c or 0x94 depending on HW]
MCG_C1 = (MCG_C1_CLKS_EXTERN_CLK | MCG_C1_FRDIV_256); // switch to external source (the FLL input clock is set to as close to its input range as possible, although this is not absolutely necessary if the FLL will not be used) [0x98]
while ((MCG_S & MCG_S_OSCINIT) == 0) {} // loop until the crystal source has been selected
while ((MCG_S & MCG_S_IREFST) != 0) {} // loop until the FLL source is no longer the internal reference clock
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXTERN_CLK) {} // loop until the external reference clock source is valid
MCG_C5 = ((CLOCK_DIV - 1) | MCG_C5_PLLSTEN0); // now move from state FEE to state PBE (or FBE) PLL remains enabled in normal stop modes [0x23]
MCG_C6 = ((CLOCK_MUL - MCG_C6_VDIV0_LOWEST) | MCG_C6_PLLS); // set the PLL multiplication factor [0x58]
while ((MCG_S & MCG_S_PLLST) == 0) {} // loop until the PLLS clock source becomes valid
while ((MCG_S & MCG_S_LOCK) == 0) {} // loop until PLL locks
SIM_CLKDIV1 = (((SYSTEM_CLOCK_DIVIDE - 1) << 28) | ((BUS_CLOCK_DIVIDE - 1) << 16)); // prepare bus clock divides [0x10010000]
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL) {} // loop until the PLL clock is selected

This is verified by the uTasker KL46 simulator below.

Further details:
http://www.utasker.com/kinetis/MCG.html

References:
http://www.utasker.com/kinetis/FRDM-KL46Z.html
http://www.utasker.com/kinetis/TWR-KL46Z48M.html

These is the user setup to achieve this in the uTasker project:
#define CRYSTAL_FREQUENCY 8000000 // 8 MHz crystal
#define CLOCK_MUL 48 // the PLL multiplication factor to achieve MCGPLLCLK operating frequency of 98MHz (x24 to x55 possible) (MCGPLLCLK/2 is 48MHz - required by USB)
#define SYSTEM_CLOCK_DIVIDE 2 // divide (1,2,3..16 possible) to get core clock of 48MHz
#define FLASH_CLOCK_DIVIDE 2 // divide from core clock for bus and flash clock (1,2,3..8 possible) 24MHz
#define OSC_LOW_GAIN_MODE // oscillator without feedback resistor or load capacitors so use low gain mode (this is removed when the crystal is loaded)

Note the option that is HW dependent!!!

Regards

Mark
Kinetis for professionals: http://www.utasker.com/kinetis.html

Re: KL46Z PLL

briceagbebe-cos — Mon, 02 Nov 2020 13:54:02 GMT

Hi,

Unfortunately it doesn't work. I did the same thing as you said.

#define CLKSTS_MASK 0x08
#define CLKST_MASK  0x0C
void BootClockRUN()
{

        MCG_C2 = 0x94;
        MCG_C1 = 0x98;

        while((MCG_S & (1<<1)) == 0){}
        
        while((MCG_S & (1<<4)) !=0){}

        while((MCG_S & CLKSTS_MASK) != CLKSTS_MASK){}

        MCG_C5 = 0x23;

        MCG_C6 = 0x58;

        while((MCG_S & (1<<5)) ==0){}
        
        while((MCG_S & (1<<6)) ==0){}

        SIM_CLKDIV1 = 0x10010000;

       while(((MCG_S & CLKST_MASK)) != CLKST_MASK){}
}‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

This is the board I have:

Any other idea ?

Thank you,

Re: KL46Z PLL

mjbcswitzerland — Mon, 07 Nov 2016 22:04:41 GMT

The FRDM-K46Z requires high-gain crystal mode (MCG_C2 = 0x9c;)

If it still doesn't start, load the binary file from the link to the FRDM-KL46Z that I gave in the previous post to check that your board runs with it. Then either use the OpenSDA debugger or the memory debug command on its command line interface (VCOM at 19200 Baud, 1 stop, 8 bits, XON/XOFF) to display internal registers to see the values that are needed.

[In the I/O menu there is a command that can be used as follows

md 400ff000 l 4      to display 4 long words from address 0x400ff000
md 400ff000 w 4    to display 4 short words from address 0x400ff000
md 400ff000 b 4      to display 4 bytes from address 0x400ff000]

If you prefer an immediate and complete solution for the FRDM-KL46Z (with USB-MSD, USB-HID, USB-CDC, USB-RNDIS and TCP/IP, SLCD, File system, nRF24L01 and most other peripherals) simply download the uTasker project.

Regards

Mark

Re: KL46Z PLL

briceagbebe-cos — Tue, 08 Nov 2016 19:34:27 GMT

Hi,

I uploaded the [ uTaskerV1.4.8_BM_FRDM_KL46Z_8080.bin ] file into my board, but again nothing happens.

I think something is wrong with my board.

Thank you for your support !

Best Regards,

Re: KL46Z PLL

mjbcswitzerland — Tue, 08 Nov 2016 20:50:25 GMT

That is the wrong file - it only works with the boot loader - you need to load either "uTaskerV1.4.8_FRDM_KL46Z.bin" or "uTaskerSerialBoot_FRDM-KL46Z_KBOOT_UART_KBOOT_HID_USBMSD.bin" for it to be able to operate.

Regards

Mark

Re: KL46Z PLL

Robin_Shen — Wed, 09 Nov 2016 01:23:10 GMT

Hi Briceag,

Please download the SDK_2.0_FRDM-KL46Z from this web.

You can refer the lptmr project.

This demo toggle LED in LPTMR interrupt every one second.

Best Regards,

Robin