topic Re: K65 IO state during power ramp in Kinetis Microcontrollers https://community.nxp.com/t5/Kinetis-Microcontrollers/K65-IO-state-during-power-ramp/m-p/632192#M38069 <HTML><HEAD></HEAD><BODY><P>The key to the default states is whether the part is above the POR threshold.</P><P>&nbsp;</P><P>On power-up, the GPIO states are indeterminate until the Power On Reset is complete at about 1V or so – the chip will be in reset at this time and enable the default bit settings. On power-down, the LVD setting will generate a reset which will make the GPIO high impedance. At the falling POR threshold the GPIO can go back to indeterminate states. The region between POR and LVD thresholds will generate a reset and make the GPIO high impedance.</P><P></P><P>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;- John S</P></BODY></HTML> Tue, 07 Mar 2017 22:19:33 GMT dkh 2017-03-07T22:19:33Z K65 IO state during power ramp https://community.nxp.com/t5/Kinetis-Microcontrollers/K65-IO-state-during-power-ramp/m-p/632191#M38068 <HTML><HEAD></HEAD><BODY><P>While the K65’s VDD is ramping (or off, even) what are the IOs doing? Tristated, weak pull-up/downs?</P></BODY></HTML> Tue, 07 Mar 2017 22:17:28 GMT https://community.nxp.com/t5/Kinetis-Microcontrollers/K65-IO-state-during-power-ramp/m-p/632191#M38068 dkh 2017-03-07T22:17:28Z Re: K65 IO state during power ramp https://community.nxp.com/t5/Kinetis-Microcontrollers/K65-IO-state-during-power-ramp/m-p/632192#M38069 <HTML><HEAD></HEAD><BODY><P>The key to the default states is whether the part is above the POR threshold.</P><P>&nbsp;</P><P>On power-up, the GPIO states are indeterminate until the Power On Reset is complete at about 1V or so – the chip will be in reset at this time and enable the default bit settings. On power-down, the LVD setting will generate a reset which will make the GPIO high impedance. At the falling POR threshold the GPIO can go back to indeterminate states. The region between POR and LVD thresholds will generate a reset and make the GPIO high impedance.</P><P></P><P>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;- John S</P></BODY></HTML> Tue, 07 Mar 2017 22:19:33 GMT https://community.nxp.com/t5/Kinetis-Microcontrollers/K65-IO-state-during-power-ramp/m-p/632192#M38069 dkh 2017-03-07T22:19:33Z