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    <title>Kinetis MicrocontrollersのトピックRe: K66 SDRAM Interface connection</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/K66-SDRAM-Interface-connection/m-p/629283#M37837</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Customer need to refer Table 35-7 about MT48LC4M16A2B4-6A SDRAM connection:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/3261i04487D2D6C6E39CA/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Customer connection is correct:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/3328iD653410A938EA971/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Wish it helps.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Ma Hui&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 26 Dec 2016 09:20:19 GMT</pubDate>
    <dc:creator>Hui_Ma</dc:creator>
    <dc:date>2016-12-26T09:20:19Z</dc:date>
    <item>
      <title>K66 SDRAM Interface connection</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/K66-SDRAM-Interface-connection/m-p/629282#M37836</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;How should I go about hooking up the SDRAM addressing lines from the K66 to the Micron part MT48LC4M16A2B4-6A IT? I am having trouble figuring it out from the K66 RM. It is a 64Mb SDRAM module organized as 1Mb x 16 x 4 banks. There are 8 column addresses, with 12 address pins and 2 bank select pins. This doesn’t match any of the specific examples in the RM, and I’m not sure I understand it well enough to hook it up right. My best guess would be as follows:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD style="border: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="193"&gt;&lt;P&gt;SDRAM Controller Pins:&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border: solid windowtext 1.0pt; border-left: none; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A9&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border: solid windowtext 1.0pt; border-left: none; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A10&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border: solid windowtext 1.0pt; border-left: none; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A11&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border: solid windowtext 1.0pt; border-left: none; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A12&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border: solid windowtext 1.0pt; border-left: none; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A13&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border: solid windowtext 1.0pt; border-left: none; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A14&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border: solid windowtext 1.0pt; border-left: none; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A15&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border: solid windowtext 1.0pt; border-left: none; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A16&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border: solid windowtext 1.0pt; border-left: none; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A17&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border: solid windowtext 1.0pt; border-left: none; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A18&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border: solid windowtext 1.0pt; border-left: none; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A19&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border: solid windowtext 1.0pt; border-left: none; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A20&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border: solid windowtext 1.0pt; border-left: none; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A21&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border: solid windowtext 1.0pt; border-left: none; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A22&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style="border: solid windowtext 1.0pt; border-top: none; padding: 0in 5.4pt 0in 5.4pt;" width="193"&gt;&lt;P&gt;SDRAM Pins:&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none; border-bottom: solid windowtext 1.0pt; border-right: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A7&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none; border-bottom: solid windowtext 1.0pt; border-right: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A6&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none; border-bottom: solid windowtext 1.0pt; border-right: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A5&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none; border-bottom: solid windowtext 1.0pt; border-right: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A4&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none; border-bottom: solid windowtext 1.0pt; border-right: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A3&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none; border-bottom: solid windowtext 1.0pt; border-right: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A2&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none; border-bottom: solid windowtext 1.0pt; border-right: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A1&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none; border-bottom: solid windowtext 1.0pt; border-right: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A0&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none; border-bottom: solid windowtext 1.0pt; border-right: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A8&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none; border-bottom: solid windowtext 1.0pt; border-right: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A9&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none; border-bottom: solid windowtext 1.0pt; border-right: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A10&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none; border-bottom: solid windowtext 1.0pt; border-right: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;A11&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none; border-bottom: solid windowtext 1.0pt; border-right: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;BA0&lt;/P&gt;&lt;/TD&gt;&lt;TD style="border-top: none; border-left: none; border-bottom: solid windowtext 1.0pt; border-right: solid windowtext 1.0pt; padding: 0in 5.4pt 0in 5.4pt;" width="80"&gt;&lt;P&gt;BA1&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is that accurate?”&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 20 Dec 2016 22:07:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/K66-SDRAM-Interface-connection/m-p/629282#M37836</guid>
      <dc:creator>eico</dc:creator>
      <dc:date>2016-12-20T22:07:01Z</dc:date>
    </item>
    <item>
      <title>Re: K66 SDRAM Interface connection</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/K66-SDRAM-Interface-connection/m-p/629283#M37837</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Customer need to refer Table 35-7 about MT48LC4M16A2B4-6A SDRAM connection:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/3261i04487D2D6C6E39CA/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Customer connection is correct:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/3328iD653410A938EA971/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Wish it helps.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Ma Hui&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 26 Dec 2016 09:20:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/K66-SDRAM-Interface-connection/m-p/629283#M37837</guid>
      <dc:creator>Hui_Ma</dc:creator>
      <dc:date>2016-12-26T09:20:19Z</dc:date>
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