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    <title>topic Re: DMA on kinetis k64 in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/DMA-on-kinetis-k64/m-p/626109#M37548</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Dean,&lt;/P&gt;&lt;P&gt;I've some question in order to understand better your answer.&lt;BR /&gt;1. OK&lt;/P&gt;&lt;P&gt;2. Imagine I've channel 0 that start and I want to link channel 1 at the end of the major loop of channel 0. So I will put the address of my edma_tcd struct in the scatter/gather option of the processor expert and it should be ok? However I think that the information in the edma_tcd struct refer to channel 1.. Is it ok?&lt;/P&gt;&lt;P&gt;3. OK&lt;/P&gt;&lt;P&gt;4. Do you mean that I have to initialize this struct maybe in the half of the transfer of channel 0? I've seen in the options of the processor expert that DMA can generate an interrupt at the half of a complete transfer instead of the end of a complete transfer. In this way I can initialize the struct in the interrupt.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance,&lt;BR /&gt;Stefano&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 14 Oct 2016 09:56:07 GMT</pubDate>
    <dc:creator>stefanobizzari</dc:creator>
    <dc:date>2016-10-14T09:56:07Z</dc:date>
    <item>
      <title>DMA on kinetis k64</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/DMA-on-kinetis-k64/m-p/626107#M37546</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm using a kinetis k64 microcontroller. In particular a MK64FN1M0VLQ12 part.&lt;/P&gt;&lt;P&gt;I need to transfer a lot of datas from memory to a peripheral (a video controller).&lt;/P&gt;&lt;P&gt;The videocontroller just need a simple initialization in order to specify the video area and then just a write pin to confirm the data.&lt;/P&gt;&lt;P&gt;So what I'm trying to do is to use a pwm in order to toggle a pin and, this pwm, is an hw trigger for a DMA channel that fetch the data and put it on the desired port.&lt;/P&gt;&lt;P&gt;The data size is of 2 bytes so the transaction count for the minor loop is 1 (2 bytes per request).&lt;BR /&gt;It works correctly except the fact that the major loop (as far as I have seen) is limited to 32767 transitions. What can I do if I need to transfer more datas?&lt;/P&gt;&lt;P&gt;I can try to re-iterate 32k transfer controlling the video size accordingly. But, in this way, the speed is reduced (every time I need to set the video size to 32767 pixels, start a new transfer etc etc).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I've seen that I can link one or more channels each other. However I've not understand how the linked channel can start "automatically"... I mean, in processor expert I've seen that there an option to link another channel at the end of a complete transfer which is great except the fact that it seems that it doesn't start the second channel.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I've attached a picture of my dma linking configuration.. What I miss in your opinion?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;And, a part of this, is there an easier way to do what I need? Maybe I'm trying to do all in a very complicated way and there is an easier solution. I'm a very newbie regarding DMA transfer so I'm afraid that I'm trying an overcomplicated solution for my problem.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Oct 2016 07:51:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/DMA-on-kinetis-k64/m-p/626107#M37546</guid>
      <dc:creator>stefanobizzari</dc:creator>
      <dc:date>2016-10-11T07:51:16Z</dc:date>
    </item>
    <item>
      <title>Re: DMA on kinetis k64</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/DMA-on-kinetis-k64/m-p/626108#M37547</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Stefano,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 15px;"&gt;The limitation of the Major Loop Size could be&amp;nbsp;settled by enabling the Scatter/Gather Processing feature of the eDMA module. To utilize the feature, we need to:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;1. Define an object/variable with the TCD type, as shown below, which takes 32 bytes.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="padding-left: 30px;"&gt;&lt;SPAN style="font-size: 12px; color: #808080;"&gt;typedef struct _edma_tcd&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 12px; color: #808080;"&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 12px; color: #808080;"&gt; __IO uint32_t SADDR; /*!&amp;lt; SADDR register, used to save source address */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 12px; color: #808080;"&gt; __IO uint16_t SOFF; /*!&amp;lt; SOFF register, save offset bytes every transfer */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 12px; color: #808080;"&gt; __IO uint16_t ATTR; /*!&amp;lt; ATTR register, source/destination transfer size and modulo */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 12px; color: #808080;"&gt; __IO uint32_t NBYTES; /*!&amp;lt; Nbytes register, minor loop length in bytes */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 12px; color: #808080;"&gt; __IO uint32_t SLAST; /*!&amp;lt; SLAST register */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 12px; color: #808080;"&gt; __IO uint32_t DADDR; /*!&amp;lt; DADDR register, used for destination address */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 12px; color: #808080;"&gt; __IO uint16_t DOFF; /*!&amp;lt; DOFF register, used for destination offset */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 12px; color: #808080;"&gt; __IO uint16_t CITER; /*!&amp;lt; CITER register, current minor loop numbers, for unfinished minor loop.*/&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 12px; color: #808080;"&gt; __IO uint32_t DLAST_SGA; /*!&amp;lt; DLASTSGA register, next stcd address used in scatter-gather mode */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 12px; color: #808080;"&gt; __IO uint16_t CSR; /*!&amp;lt; CSR register, for TCD control status */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 12px; color: #808080;"&gt; __IO uint16_t BITER; /*!&amp;lt; BITER register, begin minor loop count. */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 12px; color: #808080;"&gt;} edma_tcd_t;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 15px;"&gt;2. When&amp;nbsp;configuring the TCDn: 1)initialize the DMA_TCDn_DLASTSGA register with the address of the TCD object; 2)&amp;nbsp;s&lt;/SPAN&gt;&lt;SPAN style="font-size: 15px;"&gt;et the DMA_TCDn_CSR[ESG] bit .&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;3. Initiate&amp;nbsp;the first DMA transfer as usual.&lt;/P&gt;&lt;P&gt;4. Initialize the&amp;nbsp;&lt;SPAN&gt;TCD&amp;nbsp;object with new value based on the requirement before the current major loop&amp;nbsp;is completed.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;When the&amp;nbsp;&lt;SPAN&gt;current major &lt;/SPAN&gt;&lt;SPAN&gt;loop&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;is &lt;/SPAN&gt;&lt;SPAN&gt;completed, the eDMA engine will load the defined TCD object to the current channel TCD. Then new DMA transfer could be triggered by the following&amp;nbsp;hardware trigger, the coming PWM in your case.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #ff0000;"&gt;Note:&amp;nbsp;The TCD object address must be 0-modulo-32-byte, else a&amp;nbsp;configuration error is reported.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Dean&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 13 Oct 2016 10:50:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/DMA-on-kinetis-k64/m-p/626108#M37547</guid>
      <dc:creator>dean_jia</dc:creator>
      <dc:date>2016-10-13T10:50:52Z</dc:date>
    </item>
    <item>
      <title>Re: DMA on kinetis k64</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/DMA-on-kinetis-k64/m-p/626109#M37548</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Dean,&lt;/P&gt;&lt;P&gt;I've some question in order to understand better your answer.&lt;BR /&gt;1. OK&lt;/P&gt;&lt;P&gt;2. Imagine I've channel 0 that start and I want to link channel 1 at the end of the major loop of channel 0. So I will put the address of my edma_tcd struct in the scatter/gather option of the processor expert and it should be ok? However I think that the information in the edma_tcd struct refer to channel 1.. Is it ok?&lt;/P&gt;&lt;P&gt;3. OK&lt;/P&gt;&lt;P&gt;4. Do you mean that I have to initialize this struct maybe in the half of the transfer of channel 0? I've seen in the options of the processor expert that DMA can generate an interrupt at the half of a complete transfer instead of the end of a complete transfer. In this way I can initialize the struct in the interrupt.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance,&lt;BR /&gt;Stefano&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 14 Oct 2016 09:56:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/DMA-on-kinetis-k64/m-p/626109#M37548</guid>
      <dc:creator>stefanobizzari</dc:creator>
      <dc:date>2016-10-14T09:56:07Z</dc:date>
    </item>
    <item>
      <title>Re: DMA on kinetis k64</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/DMA-on-kinetis-k64/m-p/626110#M37549</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Stefano,&lt;/P&gt;&lt;P&gt;Here are the answers of your questions.&lt;/P&gt;&lt;P&gt;2. You do not have to use the channel linking function in case you use the&amp;nbsp;Scatter/Gather feature to solve this problem. One channel is sufficient. The mechanism&amp;nbsp;is that the eDMA engine updates the TCD automatically for the next major loop transfer after the previous transfer is end.&lt;/P&gt;&lt;P&gt;4. You can either use the interrupt method or the&amp;nbsp;&lt;SPAN&gt;Scatter/Gather method to update the TCD for a new transfer. However, as far as I'm concerned,&amp;nbsp;the&amp;nbsp;Scatter/Gather method takes less time to complete the update between the transfer interval. It is done by the eDMA engine rather than CPU. Thus, I suggest to use the&amp;nbsp;Scatter/Gather method.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Dean&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 17 Oct 2016 03:13:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/DMA-on-kinetis-k64/m-p/626110#M37549</guid>
      <dc:creator>dean_jia</dc:creator>
      <dc:date>2016-10-17T03:13:23Z</dc:date>
    </item>
    <item>
      <title>Re: DMA on kinetis k64</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/DMA-on-kinetis-k64/m-p/626111#M37550</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Helo Stefano,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;As Dean Jia already said, you can implement the Scatter/Gather feature. Here is a document and example (in baremetal implementation) that describes this features: &lt;A href="https://community.nxp.com/docs/DOC-329546"&gt;What is and how to configure the eDMA scatter/gather feature&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also, if you still want to know how the linking process between two DMA channels is, you can refer to this post (it is related to linking channels on minor loop instead of major loop but this can help you to understand the concept): &lt;A href="https://community.nxp.com/thread/435844"&gt;https://community.nxp.com/thread/435844&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope this helps!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;BR /&gt;Isaac&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 20 Oct 2016 01:11:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/DMA-on-kinetis-k64/m-p/626111#M37550</guid>
      <dc:creator>isaacavila</dc:creator>
      <dc:date>2016-10-20T01:11:26Z</dc:date>
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