K66 RMII pin MUX doesn't hold

gudmundurkristi — Mon, 19 Dec 2016 18:24:00 GMT

I've been struggling for a while with the RMII setup of K66 that is connected to TI's dp83620. The connection to the DP83620 and it's setup is the same as for another K70 project I have and that works fine. Now porting the code to the K66 gives a strange issue of PORTA_PCR5 changing from MUX setup of 4 to 6 and PORTA_PCR9 from 1 to 5. Can't see any mention of this in any documents.

IO config is:

/**
ETHERNET configuration (DP83620)
PTA24 = ETH_PCF_EN - Enable DP83620 Ethernet chip - OUTPUT (initial hi)
PTE26 = 50MHz osc input - default
PTA9 = ETH_INT - Interrupt from DP83620 Ethernet chip
PTA8 = ETH_RMII_MDC
PTA7 = ETH_RMII_MDIO
PTA17 = ETH_RMII_TXD1
PTA16 = ETH_RMII_TXD0
PTA15 = ETH_RMII_TXEN
PTA14 = ETH_RMII_CRS_DV
PTA13 = ETH_RMII_RXD0
PTA12 = ETH_RMII_RXD1
PTA5 = ETH_RMII_RXER
PTA28 = ETH_RESET output - Reset DP83620 Ethernet chip (initial lo)
**/

The setup is:

#define DEFINE_ETHERNET_IO PORTA_PCR28 = (0 | PORT_PCR_MUX(PORT_PIN_MUX_CONTROL_PIN_ALT1)); \
PTA->PCOR |= (0x01 << 28); \
PTA->PDDR |= (0x01 << 28); /* ETH_RESET as output */ \
PORTA_PCR24 = (0 | PORT_PCR_MUX(PORT_PIN_MUX_CONTROL_PIN_ALT1)); /* ETH_EN */ \
PTA->PCOR |= (0x01 << 24); /* ETH_PCF_EN = LO */ \
PTA->PDDR |= (0x01 << 24); /* ETH_PCF_EN as output */ \
PORTA_PCR9 = (0 | PORT_PCR_MUX(PORT_PIN_MUX_CONTROL_PIN_ALT1) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK); /* ETH_INT */ \
PTA->PSOR |= (0x01 << 9); /* ETH_PWRDOWN= HI */ \
PTA->PDDR |= (0x01 << 9); /* ETH_PWRDOWN as output */ \
/**/ \
PORTE->PCR[26] = (0 | PORT_PCR_MUX(PORT_PIN_MUX_CONTROL_PIN_ALT2)); /* SYS_CLK from 50MHz osc */ \
/**/ \
PORTA_PCR8 = (0 | PORT_PCR_MUX(PORT_PIN_MUX_CONTROL_PIN_ALT5) | ETH_PORT_MDC_SRE_MASK); /* ETH_RMII_MDC */ \
PORTA_PCR7 = (0 | PORT_PCR_MUX(PORT_PIN_MUX_CONTROL_PIN_ALT5) | PORT_PCR_PS_MASK | PORT_PCR_PE_MASK); /* ETH_RMII_MDIO */ \
PORTA_PCR17 = (0 | PORT_PCR_MUX(PORT_PIN_MUX_CONTROL_PIN_ALT4)); /* ETH_RMII_TXD1 */ \
PORTA_PCR16 = (0 | PORT_PCR_MUX(PORT_PIN_MUX_CONTROL_PIN_ALT4)); /* ETH_RMII_TXD0 */ \
PORTA_PCR15 = (0 | PORT_PCR_MUX(PORT_PIN_MUX_CONTROL_PIN_ALT4)); /* ETH_RMII_TXEN */ \
PORTA_PCR14 = (0 | PORT_PCR_MUX(PORT_PIN_MUX_CONTROL_PIN_ALT4)); /* ETH_RMII_CRS_DV */ \
PORTA_PCR13 = (0 | PORT_PCR_MUX(PORT_PIN_MUX_CONTROL_PIN_ALT4)); /* ETH_RMII_RXD0 */ \
PORTA_PCR12 = (0 | PORT_PCR_MUX(PORT_PIN_MUX_CONTROL_PIN_ALT4)); /* ETH_RMII_RXD1 */ \
PORTA_PCR5 = (0 | PORT_PCR_MUX(PORT_PIN_MUX_CONTROL_PIN_ALT4)); /* ETH_RMII_RXER */

Ethernet receives packages like ping and replies to it internally (I can see action on the ETH_TX0, ETH_TX1 & ETH_TXEN and ENET cout's up transmissions while nothing is released to the wire). the PHY is not in isolate mode nor in loopback mode so it isn't that.

The strange thing is that if I print out the registers for pinout mux setup it replies:

SIM_SCGC2....: 0x00000001
PORTA_PCR24: 0x00000100, ISF:0, IRQC:0, LK:0, MUX:1, DSE:0, ODE:0, PFE:0, SRE:0, PE:0, PS0
GPIOA_PCOR...: 0x00000000
GPIOA_PSOR...: 0x00000000
GPIOA_PDDR...: 0x11000E00
PORTE_PCR26: 0x00000202, ISF:0, IRQC:0, LK:0, MUX:2, DSE:0, ODE:0, PFE:0, SRE:0, PE:1, PS0
PORTA_PCR9.: 0x00000503, ISF:0, IRQC:0, LK:0, MUX:5, DSE:0, ODE:0, PFE:0, SRE:0, PE:1, PS1
PORTA_PCR8.: 0x00000500, ISF:0, IRQC:0, LK:0, MUX:5, DSE:0, ODE:0, PFE:0, SRE:0, PE:0, PS0
PORTA_PCR7.: 0x00000503, ISF:0, IRQC:0, LK:0, MUX:5, DSE:0, ODE:0, PFE:0, SRE:0, PE:1, PS1
PORTA_PCR17: 0x00000400, ISF:0, IRQC:0, LK:0, MUX:4, DSE:0, ODE:0, PFE:0, SRE:0, PE:0, PS0
PORTA_PCR16: 0x00000400, ISF:0, IRQC:0, LK:0, MUX:4, DSE:0, ODE:0, PFE:0, SRE:0, PE:0, PS0
PORTA_PCR15: 0x00000400, ISF:0, IRQC:0, LK:0, MUX:4, DSE:0, ODE:0, PFE:0, SRE:0, PE:0, PS0
PORTA_PCR14: 0x00000400, ISF:0, IRQC:0, LK:0, MUX:4, DSE:0, ODE:0, PFE:0, SRE:0, PE:0, PS0
PORTA_PCR13: 0x00000400, ISF:0, IRQC:0, LK:0, MUX:4, DSE:0, ODE:0, PFE:0, SRE:0, PE:0, PS0
PORTA_PCR12: 0x00000400, ISF:0, IRQC:0, LK:0, MUX:4, DSE:0, ODE:0, PFE:0, SRE:0, PE:0, PS0
PORTA_PCR5.: 0x00000603, ISF:0, IRQC:0, LK:0, MUX:6, DSE:0, ODE:0, PFE:0, SRE:0, PE:1, PS1
PORTA_PCR28.: 0x00000100, ISF:0, IRQC:0, LK:0, MUX:1, DSE:0, ODE:0, PFE:0, SRE:0, PE:0, PS0

Does anyone out there have an idea of what this could be?

here is the ENET register setup:

ENET Register Block
---------------------------------
ENET_EIR.: 1C000000
ENET_EIMR: 0E000000
ENET_RDAR: 01000000
ENET_TDAR: 00000000
ENET_ECR.: F0000002 - Ethernet Control Register
ENET_MMFR: 60E3FFFF
ENET_MSCR: 00000048 - MII Speed Control Register
ENET_MIBC: 40000000 - MIB Control Register
ENET_RCR.: 05F05104 - Receive Control Register
ENET_TCR.: 00000104 - Transmit Control Register
ENET_PALR: 00603522 - Physical Address Lower Register
ENET_PAUR: 41478808 - Physical Address Upper Register
ENET_OPD.: 00010000 - Opcode/Pause Duration Register
ENET_IAUR: 00000000 - Descriptor Individual Upper Address Register
ENET_IALR: 00000400 - Descriptor Individual Lower Address Register
ENET_GAUR: 00000000 - Descriptor Group Upper Address Register
ENET_GALR: 00000000 - Descriptor Group Lower Address Register
ENET_TFWR: 00000100 - Transmit FIFO Watermark Register
ENET_RDSR: 1FFF0040 - Receive Descriptor Ring Start Register
ENET_TDSR: 1FFF0000 - Transmit Buffer Descriptor Ring Start Register
ENET_MRBR: 00000640 - Maximum Receive Buffer Size Register
ENET_RSFL: 00000000 - Receive FIFO Selection Full Threshold
ENET_RSEM: 00000000 - Receive FIFO Section Empty Threshold
ENET_RAEM: 00000004 - Receive FIFO Almost Empty Threshold
ENET_RAFL: 00000004 - Receive FIFO Almost Full Threshold
ENET_TSEM: 00000000 - Transmit FIFO Section Empty Threshold
ENET_TAEM: 0000000C - Transmit FIFO Almost Empty Threshold
ENET_TAFL: 00000008 - Transmit FIFO Almost Full Threshold
ENET_TIPG: 0000000C - Transmit Inter-Packet Gap
ENET_FTRL: 000007FF - Frame Truncation Length
ENET_TACC: 00000010 - Transmit Accelerator Function Configuration
ENET_RACC: 00000047 - Receive Accelerator Function Configuration
---------------------------------

Best regards,

Mummi

Re: K66 RMII pin MUX doesn't hold

Hui_Ma — Wed, 21 Dec 2016 00:58:01 GMT

I do a test with FRDM-K66F board & KDSK V2.0 software, while I don't find your mentioned issue.

I also check the K66 errata record, without any record similar with this issue.

Could you check your software if there exist code modify the PORTA_PCR5 & PORTA_PCR9 registers value after the Ethernet pin initialization?

If possible, you could debug the code and check those register value setting if as expected.

And during the code execution to find where the code change those registers.

Wish it helps.

Have a great day,
Ma Hui
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K66 RMII pin MUX doesn't hold

Re: K66 RMII pin MUX doesn't hold