MKE04 bus clock & UART speed

nickkelsey — Wed, 19 Apr 2017 19:31:02 GMT

The MKE04 UART baud rate seems to be exactly twice has fast as it should be.

System clock is 48MHz (internal clock source, BDIV set to 0 in startup code, otherwise default).

The UART is clocked by the Bus Clock according to the documentation.

Bus clock is assumed to be 24MHz as the documentation states it is System Clock / 2, max 24MHz.

UART baud rate modulo divisor (SBR aka BR) is set to 13.

24Mhz / 16 / 13 = ~115200bps.

Sending repeated 0x00 results in a low period of 39.0us and a high period of 4.4us.

low period = 1 start bit + 8 data bits = 9 bits, 39.0us / 9 = 4.333us

4.333us = 230769bps

Working in reverse: The documentation on the SBR (aka BR) register states the UART baud rate equals BUSCLK/(16xBR).

so 230769kbps = BUSCLK/(16x13) therefore we can calculate BUSCLK = 48,000,000 = 48MHz.

Something is out be a factor of 2.

Spitballing possible causes:

A) UART setting isn't Bus Clock / 16 but Bus Clock / 8 (unlikely as UARTs are typically 16x oversampled).

B) UART is clocked from the System Clock, not the Bus Clock (documentation would have to be wrong in lots of places).

C) The Bus Clock really is operating at 48MHz, same as the System Clock (not div 2).

D) The Bus Clock really is operating at 48MHz and the System Clock is somehow operating at 96MHz. This is unlikely as a GPIO toggle with NOP delays suggests the core is operating at 48MHz.

This is the 16-pin version of the part so there is no BUSOUT pin to verify.

Looking for assistance.

Thanks

Re: MKE04 bus clock & UART speed

nickkelsey — Wed, 19 Apr 2017 21:07:11 GMT

Figured out the problem... need to set DIV2 to set the bus clock as system clock / 2 (answer C in my first post).

In the block diagram DIV2 refers to the DIV2 configuration bit, not divide by 2.

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MKE04 bus clock & UART speed

Re: MKE04 bus clock & UART speed