topic Re: K64F instruction cache operation in Kinetis Microcontrollers https://community.nxp.com/t5/Kinetis-Microcontrollers/K64F-instruction-cache-operation/m-p/621947#M37223 <HTML><HEAD></HEAD><BODY><P>Found instruction cache described in&nbsp;K64 Sub-Family Reference Manual, chapter 28, Flash Memory Controller (FMC).</P><P>&nbsp;</P></BODY></HTML> Wed, 08 Mar 2017 06:48:00 GMT adriangogu 2017-03-08T06:48:00Z K64F instruction cache operation https://community.nxp.com/t5/Kinetis-Microcontrollers/K64F-instruction-cache-operation/m-p/621946#M37222 <HTML><HEAD></HEAD><BODY><P>Hello,</P><P></P><P>I am using FRDM-K64F module.</P><P>Found in ARM documentation a note telling: "A small caching component is present in the Cortex-M3 and Cortex-M4 processors to accelerate flash memory accesses during instruction fetches."</P><P>Referring to this note&nbsp;I would&nbsp;ask whether such instruction cache component&nbsp;is implemented within K64 microcontroller.</P><P>Could you please indicate documentation describing the operation / configuration of the mentioned instruction cache ?</P><P>For application code profiling accuracy, I would be interested to know if instruction cache usage can&nbsp;be disabled/bypassed ?</P><P></P><P>Thank you.</P><P>Best Regards,</P><P>Adrian</P></BODY></HTML> Mon, 06 Mar 2017 14:39:34 GMT https://community.nxp.com/t5/Kinetis-Microcontrollers/K64F-instruction-cache-operation/m-p/621946#M37222 adriangogu 2017-03-06T14:39:34Z Re: K64F instruction cache operation https://community.nxp.com/t5/Kinetis-Microcontrollers/K64F-instruction-cache-operation/m-p/621947#M37223 <HTML><HEAD></HEAD><BODY><P>Found instruction cache described in&nbsp;K64 Sub-Family Reference Manual, chapter 28, Flash Memory Controller (FMC).</P><P>&nbsp;</P></BODY></HTML> Wed, 08 Mar 2017 06:48:00 GMT https://community.nxp.com/t5/Kinetis-Microcontrollers/K64F-instruction-cache-operation/m-p/621947#M37223 adriangogu 2017-03-08T06:48:00Z