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    <title>topic Re: K22F10MA interrupts issue in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/K22F10MA-interrupts-issue/m-p/606988#M35812</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;You disable the IRQ in the NVIC before clearing the interrupt condition.&amp;nbsp; This likely sets the 'pending' flag in the NVIC (level-triggered interrupt mode), and while I have no knowledge of the 'INT_SYS_EnableIRQ' process in your environment, I suspect when that is invoked 'later' it fails to clear the pending bit before said actual enable [NVICISERx = 1&amp;lt;&amp;lt;(y%32);] with an appropriate NVICICPRx = 1&amp;lt;&amp;lt;(y%32);&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 01 Mar 2017 13:54:12 GMT</pubDate>
    <dc:creator>egoodii</dc:creator>
    <dc:date>2017-03-01T13:54:12Z</dc:date>
    <item>
      <title>K22F10MA interrupts issue</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/K22F10MA-interrupts-issue/m-p/606987#M35811</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am working on K22f10MA kinetics controller and also using quantum leaps framework for coding. The question is whenever i get external interrupt once, its going to ISR &lt;STRONG&gt;twice&lt;/STRONG&gt;. code and result is given below.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/******* code **********/&lt;/P&gt;&lt;P&gt;uint32_t isr_array[100] ={ 0 };&lt;BR /&gt;uint8_t arraycounter = 0;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;void IR_PORTC_IRQ_ISR_Handler(void)&lt;BR /&gt;{&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; isr_array[arraycounter] = PORT_RD_ISFR(PORTC_BASE_PTR);&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; arraycounter++;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;INT_SYS_DisableIRQ(g_portIrqId[PORTC_ID]);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; Pit_start();&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; PORT_WR_ISFR(PORTC_BASE_PTR, ~0U);&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;note:&lt;/STRONG&gt; interrupt is again enabled in timer ISR. Before interrupt is enabled, clearing ISFR register.&lt;/P&gt;&lt;P&gt;/******** results ********/&lt;/P&gt;&lt;P&gt;Name : isr_array&lt;BR /&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;Details:{4, 0, 4, 0, 4, 0, 4, 0, 4, 0, 4,}&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. Why execution is going into the ISR when no interrupt detected (read 0 from ISFR register), also interrupt flag is cleared.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please help to understand what might be happening?&lt;/P&gt;&lt;P&gt;Thank you in advance.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regared,&lt;/P&gt;&lt;P&gt;Aniket&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Mar 2017 06:09:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/K22F10MA-interrupts-issue/m-p/606987#M35811</guid>
      <dc:creator>aniketmarkande</dc:creator>
      <dc:date>2017-03-01T06:09:49Z</dc:date>
    </item>
    <item>
      <title>Re: K22F10MA interrupts issue</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/K22F10MA-interrupts-issue/m-p/606988#M35812</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;You disable the IRQ in the NVIC before clearing the interrupt condition.&amp;nbsp; This likely sets the 'pending' flag in the NVIC (level-triggered interrupt mode), and while I have no knowledge of the 'INT_SYS_EnableIRQ' process in your environment, I suspect when that is invoked 'later' it fails to clear the pending bit before said actual enable [NVICISERx = 1&amp;lt;&amp;lt;(y%32);] with an appropriate NVICICPRx = 1&amp;lt;&amp;lt;(y%32);&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Mar 2017 13:54:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/K22F10MA-interrupts-issue/m-p/606988#M35812</guid>
      <dc:creator>egoodii</dc:creator>
      <dc:date>2017-03-01T13:54:12Z</dc:date>
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