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    <title>topic Re: Vhys in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Vhys/m-p/602579#M35413</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Vih and Vil are the 'guaranteed' voltage points beyond which the logic-state of the pin can be assured to be properly interpreted.&amp;nbsp; Between Vih and Vil the evaluation of the input as a binary-state depends entirely on the exact 'doping' of the PMOS and NMOS transistors in the input stage.&amp;nbsp; Any one pin, on any of a range of devices, could expect to have a 'transition point' anywhere between those guaranteed Vih and Vil limits.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Vhys is entirely different.&amp;nbsp; It is a measure of the amount of 'positive feedback' around the input-stage that will help keep the 'current binary-state' a little beyond the aforementioned 'exact voltage' where any one particular input stage is balanced between '1' and '0' levels, as defined previously.&amp;nbsp; Vhys is there to guarantee that the input stage does not go 'truly linear' at that point, AND that the input can thus reject 'some' noise without creating a 'noisy' input state.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 11 Apr 2017 17:09:06 GMT</pubDate>
    <dc:creator>egoodii</dc:creator>
    <dc:date>2017-04-11T17:09:06Z</dc:date>
    <item>
      <title>Vhys</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Vhys/m-p/602578#M35412</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am reading K24P144M120SF5. at section 2.2.1 table 1.&amp;nbsp;&lt;/P&gt;&lt;P&gt;VIH for 2.7V&amp;lt;Vdd&amp;lt;3.6V is 0.7*Vdd.&amp;nbsp;&lt;/P&gt;&lt;P&gt;ViL is 0.35Vdd.&amp;nbsp;&lt;/P&gt;&lt;P&gt;per my understanding of hysteresis, based on Vih and Vil, the Vhys should be 0.35*Vdd.&amp;nbsp;&lt;/P&gt;&lt;P&gt;could any one explain why Vhys specified in this table is 0.06*Vdd?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;David Sun&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Apr 2017 16:02:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Vhys/m-p/602578#M35412</guid>
      <dc:creator>davidsunsun</dc:creator>
      <dc:date>2017-04-11T16:02:49Z</dc:date>
    </item>
    <item>
      <title>Re: Vhys</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Vhys/m-p/602579#M35413</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Vih and Vil are the 'guaranteed' voltage points beyond which the logic-state of the pin can be assured to be properly interpreted.&amp;nbsp; Between Vih and Vil the evaluation of the input as a binary-state depends entirely on the exact 'doping' of the PMOS and NMOS transistors in the input stage.&amp;nbsp; Any one pin, on any of a range of devices, could expect to have a 'transition point' anywhere between those guaranteed Vih and Vil limits.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Vhys is entirely different.&amp;nbsp; It is a measure of the amount of 'positive feedback' around the input-stage that will help keep the 'current binary-state' a little beyond the aforementioned 'exact voltage' where any one particular input stage is balanced between '1' and '0' levels, as defined previously.&amp;nbsp; Vhys is there to guarantee that the input stage does not go 'truly linear' at that point, AND that the input can thus reject 'some' noise without creating a 'noisy' input state.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Apr 2017 17:09:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Vhys/m-p/602579#M35413</guid>
      <dc:creator>egoodii</dc:creator>
      <dc:date>2017-04-11T17:09:06Z</dc:date>
    </item>
    <item>
      <title>Re: Vhys</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Vhys/m-p/602580#M35414</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you for your prompt response, and the detailed explaining, I think I have clear understanding of this levels now.&amp;nbsp;&lt;/P&gt;&lt;P&gt;David Sun&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Apr 2017 17:36:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Vhys/m-p/602580#M35414</guid>
      <dc:creator>davidsunsun</dc:creator>
      <dc:date>2017-04-11T17:36:28Z</dc:date>
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