<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>Kinetis MicrocontrollersのトピックADC trigger via FTM2 doesn't work</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/ADC-trigger-via-FTM2-doesn-t-work/m-p/602086#M35369</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello everybody&lt;/P&gt;&lt;P&gt;I'm using MKE04Z128VLH4 MCU, and I've some problems: I'm using ADHWT trigger source with FTM2 init trigger (0b010). I configured channels CH0 e CH1 of FTM2 in combined Mode, and I used FTM0 as Trigger1 for PWM synchronization. In the register FTM2_EXTTRIG I've setted INITTRIGEN bit, so I excpeted that every period of FTM2 there's an ADC interrupt, but there's NOT!&lt;/P&gt;&lt;P&gt;I've tried to change ADHWT to FTM2 matching, and I've changed bits in the FTM2_EXTTRIG register, but there's no solution: it doesn't work.&lt;/P&gt;&lt;P&gt;PWM signals are OK, but I can't synchronize ADC conversion with FTM2 timer and I don't know why.&lt;/P&gt;&lt;P&gt;Here's FTM2 initialization.&lt;/P&gt;&lt;P&gt;As you can see I use only channel 0 and channel 1.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;void FTM2_Init(void)&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt;{&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; /* Fault control disabled for all channels ,&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; write protection disabled, FTM enabled */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_MODE = FTM_MODE_FAULTM(0b00) | FTM_MODE_WPDIS_MASK | FTM_MODE_FTMEN_MASK;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* FTM functional in debug mode */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_CONF = FTM_CONF_BDMMODE(0b11);&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Initial value of the FTM counter */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_CNTIN = 0x00000000;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; /* Modulo value of the FTM counter set according to PWM_MODULO macro&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; value */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_MOD = (PWM_PERIOD &amp;lt;&amp;lt; 2) - 1;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* High-true pulses (set on channel (n) match, clear on channel (n+1)&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; match) */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_C0SC = FTM_CnSC_ELSB_MASK;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_C1SC = FTM_CnSC_ELSB_MASK;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C2SC = FTM_CnSC_ELSB_MASK;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C3SC = FTM_CnSC_ELSB_MASK;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C4SC = FTM_CnSC_ELSB_MASK;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C5SC = FTM_CnSC_ELSB_MASK;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Trigger 1 enabled, OUTMASK register is updated by the PWM synchronization,&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; the maximum loading point is enabled */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNC = FTM_SYNC_TRIG1_MASK | FTM_SYNC_SYNCHOM_MASK | FTM_SYNC_CNTMAX_MASK;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Fault disabled, PWM synchronization enabled, dead time insertion enabled,&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; combine feature enabled, and complementary mode enabled for all channel&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; pairs */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_COMBINE |= FTM_COMBINE_COMBINE0_MASK | FTM_COMBINE_COMP0_MASK | FTM_COMBINE_DTEN0_MASK | FTM_COMBINE_SYNCEN0_MASK; // Abilito il Combine, Complementarità e dead time per coppia canali 0-1 &lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_COMBINE |= FTM_COMBINE_COMBINE1_MASK | FTM_COMBINE_COMP1_MASK | FTM_COMBINE_DTEN1_MASK | FTM_COMBINE_SYNCEN1_MASK; // Abilito il Combine, Complementarità e dead time per coppia canali 2-3 &lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_COMBINE |= FTM_COMBINE_COMBINE2_MASK | FTM_COMBINE_COMP2_MASK | FTM_COMBINE_DTEN2_MASK | FTM_COMBINE_SYNCEN2_MASK; // Abilito il Combine, Complementarità e dead time per coppia canali 4-5&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; /* Dead time prescaler 1 (system clock div. by 1), dead time value set&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; according to PWM_DEADTIME macro value */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_DEADTIME = FTM_DEADTIME_DTPS(0b00) + FTM_DEADTIME_DTVAL(0b000001); //Il bus clock alimenta FTM2 (24MHz). 0x0A -&amp;gt; 400ns deadtime&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Initialization trigger enabled */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_EXTTRIG = FTM_EXTTRIG_INITTRIGEN_MASK;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_EXTTRIG = FTM_EXTTRIG_CH0TRIG_MASK;&lt;/EM&gt;&lt;BR /&gt; &lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; /* Even (high-side) channels active low, odd (low-side) channels active&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; high */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_POL = FTM_POL_POL4_MASK | FTM_POL_POL2_MASK | FTM_POL_POL0_MASK;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* HW trigger activates SWOCTRL, OUTMASK register synchronization,&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; and FTM counter synchronization; software trigger activates SWOCTRL,&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; OUTMASK, MOD, CNTIN, CV register synchronization; enhanced PWM&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; synchronization mode selected; SWOCTRL register is updated by the PWM&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; synchronization; FTM does not clear the TRIG1 bit when HW trigger 1 is&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; detected */&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;FTM2_SYNCONF |= FTM_SYNCONF_SYNCMODE_MASK; //Enhanced PWM synchronization is selected&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_SWWRBUF_MASK; //The software trigger activates MOD, CNTIN, and CV registers synchronization&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_HWRSTCNT_MASK; //A hardware trigger activates the FTM counter synchronization&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_HWSOC_MASK; //A hardware trigger activates the SWOCTRL register synchronization&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_HWOM_MASK; //A hardware trigger activates the OUTMASK register synchronization&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_HWTRIGMODE_MASK; //FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_SWSOC_MASK; //The software trigger activates the SWOCTRL register synchronization&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_SWOM_MASK; //The software trigger activates the OUTMASK register synchronization&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_SWOC_MASK; //SWOCTRL register is updated with its buffer value by the PWM synchronization&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; /* All channels masked (forced to inactive state) */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_OUTMASK = FTM_OUTMASK_CH5OM_MASK | FTM_OUTMASK_CH4OM_MASK | FTM_OUTMASK_CH3OM_MASK | FTM_OUTMASK_CH2OM_MASK | FTM_OUTMASK_CH1OM_MASK | FTM_OUTMASK_CH0OM_MASK;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Fault input filter disabled, fault inputs 1 */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_FLTPOL = FTM_FLTPOL_FLT1POL_MASK ; //Uno 0 sull'input genera il Fault&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; Attesa_mul_2us(50);&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_FLTCTRL = FTM_FLTCTRL_FAULT1EN_MASK ;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_FMS = 0x00000000; //Eventuali Fault Flags puliti...&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Update of FTM settings */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_CNT = 1;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* System clock div. by 1 selected as FTM source clock */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SC = FTM_SC_CLKS(1) | FTM_SC_PS(0);&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Set zero duty cycle */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_C0V = 0x0000;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_C1V = 0x0000;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C2V = 0x0000;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C3V = 0x0000;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C4V = 0x0000;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C5V = 0x0000;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Update OUTMASK, SWOCTRL, and CV by software trigger */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNC |= FTM_SYNC_SWSYNC_MASK;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Enable loading of the CV registers with their buffered values */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_PWMLOAD |= FTM_PWMLOAD_LDOK_MASK;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;During MCU initialization (&lt;STRONG&gt;before&lt;/STRONG&gt; FTM2_INIT function):&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;SIM_SOPT0 |= SIM_SOPT0_ADHWT(0b010); //FTM2 init trigger ADC conversion&lt;/EM&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the main program I wrote:&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 13px;"&gt;&lt;EM&gt; FTM0_CNT = 0;&lt;/EM&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 13px;"&gt;&lt;EM&gt; FTM2_CNT = 0;&lt;/EM&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 13px;"&gt;&lt;EM&gt; FTM2_C1V = 0x20;&lt;/EM&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 13px;"&gt;&lt;EM&gt; FTM2_SYNC |= FTM_SYNC_SWSYNC_MASK; //SW updates&lt;/EM&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 13px;"&gt;&lt;EM&gt; FTM2_PWMLOAD |= FTM_PWMLOAD_LDOK_MASK;&lt;/EM&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;After this instructions I can see output on CH0 e CH1 pins of FTM2, but there's no ADC interrupt generation.&lt;/P&gt;&lt;P&gt;I've tried to change ADHWT to 0b011 value (FTM2 matching) and to change EXTTRIG register of FTM2, but I can't obtain what I want.&lt;/P&gt;&lt;P&gt;Any idea?&lt;/P&gt;&lt;P&gt;Thank you very much.&lt;/P&gt;&lt;P&gt;Roberto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 08 Sep 2016 14:47:25 GMT</pubDate>
    <dc:creator>robertogiovinet</dc:creator>
    <dc:date>2016-09-08T14:47:25Z</dc:date>
    <item>
      <title>ADC trigger via FTM2 doesn't work</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/ADC-trigger-via-FTM2-doesn-t-work/m-p/602086#M35369</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello everybody&lt;/P&gt;&lt;P&gt;I'm using MKE04Z128VLH4 MCU, and I've some problems: I'm using ADHWT trigger source with FTM2 init trigger (0b010). I configured channels CH0 e CH1 of FTM2 in combined Mode, and I used FTM0 as Trigger1 for PWM synchronization. In the register FTM2_EXTTRIG I've setted INITTRIGEN bit, so I excpeted that every period of FTM2 there's an ADC interrupt, but there's NOT!&lt;/P&gt;&lt;P&gt;I've tried to change ADHWT to FTM2 matching, and I've changed bits in the FTM2_EXTTRIG register, but there's no solution: it doesn't work.&lt;/P&gt;&lt;P&gt;PWM signals are OK, but I can't synchronize ADC conversion with FTM2 timer and I don't know why.&lt;/P&gt;&lt;P&gt;Here's FTM2 initialization.&lt;/P&gt;&lt;P&gt;As you can see I use only channel 0 and channel 1.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;void FTM2_Init(void)&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt;{&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; /* Fault control disabled for all channels ,&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; write protection disabled, FTM enabled */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_MODE = FTM_MODE_FAULTM(0b00) | FTM_MODE_WPDIS_MASK | FTM_MODE_FTMEN_MASK;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* FTM functional in debug mode */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_CONF = FTM_CONF_BDMMODE(0b11);&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Initial value of the FTM counter */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_CNTIN = 0x00000000;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; /* Modulo value of the FTM counter set according to PWM_MODULO macro&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; value */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_MOD = (PWM_PERIOD &amp;lt;&amp;lt; 2) - 1;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* High-true pulses (set on channel (n) match, clear on channel (n+1)&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; match) */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_C0SC = FTM_CnSC_ELSB_MASK;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_C1SC = FTM_CnSC_ELSB_MASK;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C2SC = FTM_CnSC_ELSB_MASK;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C3SC = FTM_CnSC_ELSB_MASK;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C4SC = FTM_CnSC_ELSB_MASK;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C5SC = FTM_CnSC_ELSB_MASK;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Trigger 1 enabled, OUTMASK register is updated by the PWM synchronization,&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; the maximum loading point is enabled */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNC = FTM_SYNC_TRIG1_MASK | FTM_SYNC_SYNCHOM_MASK | FTM_SYNC_CNTMAX_MASK;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Fault disabled, PWM synchronization enabled, dead time insertion enabled,&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; combine feature enabled, and complementary mode enabled for all channel&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; pairs */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_COMBINE |= FTM_COMBINE_COMBINE0_MASK | FTM_COMBINE_COMP0_MASK | FTM_COMBINE_DTEN0_MASK | FTM_COMBINE_SYNCEN0_MASK; // Abilito il Combine, Complementarità e dead time per coppia canali 0-1 &lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_COMBINE |= FTM_COMBINE_COMBINE1_MASK | FTM_COMBINE_COMP1_MASK | FTM_COMBINE_DTEN1_MASK | FTM_COMBINE_SYNCEN1_MASK; // Abilito il Combine, Complementarità e dead time per coppia canali 2-3 &lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_COMBINE |= FTM_COMBINE_COMBINE2_MASK | FTM_COMBINE_COMP2_MASK | FTM_COMBINE_DTEN2_MASK | FTM_COMBINE_SYNCEN2_MASK; // Abilito il Combine, Complementarità e dead time per coppia canali 4-5&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; /* Dead time prescaler 1 (system clock div. by 1), dead time value set&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; according to PWM_DEADTIME macro value */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_DEADTIME = FTM_DEADTIME_DTPS(0b00) + FTM_DEADTIME_DTVAL(0b000001); //Il bus clock alimenta FTM2 (24MHz). 0x0A -&amp;gt; 400ns deadtime&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Initialization trigger enabled */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_EXTTRIG = FTM_EXTTRIG_INITTRIGEN_MASK;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_EXTTRIG = FTM_EXTTRIG_CH0TRIG_MASK;&lt;/EM&gt;&lt;BR /&gt; &lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; /* Even (high-side) channels active low, odd (low-side) channels active&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; high */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_POL = FTM_POL_POL4_MASK | FTM_POL_POL2_MASK | FTM_POL_POL0_MASK;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* HW trigger activates SWOCTRL, OUTMASK register synchronization,&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; and FTM counter synchronization; software trigger activates SWOCTRL,&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; OUTMASK, MOD, CNTIN, CV register synchronization; enhanced PWM&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; synchronization mode selected; SWOCTRL register is updated by the PWM&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; synchronization; FTM does not clear the TRIG1 bit when HW trigger 1 is&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; detected */&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;FTM2_SYNCONF |= FTM_SYNCONF_SYNCMODE_MASK; //Enhanced PWM synchronization is selected&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_SWWRBUF_MASK; //The software trigger activates MOD, CNTIN, and CV registers synchronization&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_HWRSTCNT_MASK; //A hardware trigger activates the FTM counter synchronization&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_HWSOC_MASK; //A hardware trigger activates the SWOCTRL register synchronization&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_HWOM_MASK; //A hardware trigger activates the OUTMASK register synchronization&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_HWTRIGMODE_MASK; //FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_SWSOC_MASK; //The software trigger activates the SWOCTRL register synchronization&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_SWOM_MASK; //The software trigger activates the OUTMASK register synchronization&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNCONF |= FTM_SYNCONF_SWOC_MASK; //SWOCTRL register is updated with its buffer value by the PWM synchronization&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; /* All channels masked (forced to inactive state) */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_OUTMASK = FTM_OUTMASK_CH5OM_MASK | FTM_OUTMASK_CH4OM_MASK | FTM_OUTMASK_CH3OM_MASK | FTM_OUTMASK_CH2OM_MASK | FTM_OUTMASK_CH1OM_MASK | FTM_OUTMASK_CH0OM_MASK;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Fault input filter disabled, fault inputs 1 */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_FLTPOL = FTM_FLTPOL_FLT1POL_MASK ; //Uno 0 sull'input genera il Fault&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; Attesa_mul_2us(50);&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_FLTCTRL = FTM_FLTCTRL_FAULT1EN_MASK ;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_FMS = 0x00000000; //Eventuali Fault Flags puliti...&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Update of FTM settings */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_CNT = 1;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* System clock div. by 1 selected as FTM source clock */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SC = FTM_SC_CLKS(1) | FTM_SC_PS(0);&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Set zero duty cycle */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_C0V = 0x0000;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_C1V = 0x0000;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C2V = 0x0000;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C3V = 0x0000;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C4V = 0x0000;&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; //FTM2_C5V = 0x0000;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Update OUTMASK, SWOCTRL, and CV by software trigger */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_SYNC |= FTM_SYNC_SWSYNC_MASK;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;/* Enable loading of the CV registers with their buffered values */&lt;/EM&gt;&lt;BR /&gt;&lt;EM style="font-size: 13px;"&gt; FTM2_PWMLOAD |= FTM_PWMLOAD_LDOK_MASK;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;During MCU initialization (&lt;STRONG&gt;before&lt;/STRONG&gt; FTM2_INIT function):&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;EM style="font-size: 13px;"&gt;SIM_SOPT0 |= SIM_SOPT0_ADHWT(0b010); //FTM2 init trigger ADC conversion&lt;/EM&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the main program I wrote:&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 13px;"&gt;&lt;EM&gt; FTM0_CNT = 0;&lt;/EM&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 13px;"&gt;&lt;EM&gt; FTM2_CNT = 0;&lt;/EM&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 13px;"&gt;&lt;EM&gt; FTM2_C1V = 0x20;&lt;/EM&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 13px;"&gt;&lt;EM&gt; FTM2_SYNC |= FTM_SYNC_SWSYNC_MASK; //SW updates&lt;/EM&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN style="font-size: 13px;"&gt;&lt;EM&gt; FTM2_PWMLOAD |= FTM_PWMLOAD_LDOK_MASK;&lt;/EM&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;After this instructions I can see output on CH0 e CH1 pins of FTM2, but there's no ADC interrupt generation.&lt;/P&gt;&lt;P&gt;I've tried to change ADHWT to 0b011 value (FTM2 matching) and to change EXTTRIG register of FTM2, but I can't obtain what I want.&lt;/P&gt;&lt;P&gt;Any idea?&lt;/P&gt;&lt;P&gt;Thank you very much.&lt;/P&gt;&lt;P&gt;Roberto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Sep 2016 14:47:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/ADC-trigger-via-FTM2-doesn-t-work/m-p/602086#M35369</guid>
      <dc:creator>robertogiovinet</dc:creator>
      <dc:date>2016-09-08T14:47:25Z</dc:date>
    </item>
    <item>
      <title>Re: ADC trigger via FTM2 doesn't work</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/ADC-trigger-via-FTM2-doesn-t-work/m-p/602087#M35370</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello everybody&lt;/P&gt;&lt;P&gt;I found what was the matter&lt;/P&gt;&lt;P&gt;In the ADC settings I've used FIFO mode, so I've forgot to set&amp;nbsp;HTRGMASKE bit in ADC_SC5 and&amp;nbsp;HTRGME bit in ADC_SC4. I don't know why I made a mistake like this.&lt;/P&gt;&lt;P&gt;In this way it works!&lt;/P&gt;&lt;P&gt;Thank you!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Sep 2016 09:15:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/ADC-trigger-via-FTM2-doesn-t-work/m-p/602087#M35370</guid>
      <dc:creator>robertogiovinet</dc:creator>
      <dc:date>2016-09-09T09:15:43Z</dc:date>
    </item>
  </channel>
</rss>

