topic Re: Watchdog configuration in MKMxxZxxACxx5RM in Kinetis Microcontrollers

Watchdog configuration in MKMxxZxxACxx5RM

dmartinez1 — Tue, 25 Oct 2016 15:48:01 GMT

Hi, i am trying to do working the Watchdog Timer in a microcontroller of the family MKMxxZxxACxx5RM. The driver libraries which i am using is KM128SWDRV_R4_0_0_CW.
Currently my clock configuration is:

SIM_Init (SIM_MODULE_ALL_PERIPH_ON_CONFIG);
/* clock mode 1:1:1, 24MHz */
SIM_SetClkMode (SYSCLK_MODE0);
SIM_SetClkDiv (SYSCLK_DIV1);
FLL_Init (FLL_MODULE_FEI_24MHZ_CONFIG);

At first, i was using the test example of the libraries.

SIM_Init (SIM_MODULE_ALL_PERIPH_ON_CONFIG);

/* Watchdog timeout is of 1.5 sec approximately */
WDOG_Init(WDOG_MODULE_NORMAL_STOP_DI_CONFIG(WDOG_LPO_CLK,WDOG_DIV1,1500));

It's watched that the code didn't jump to reset, so i started investigate about it. The registers seem be all right except the register of timeout. It's been seen that it doesn't count. I think the clock sign doesn't arrive to the Watchdog but i don't know the reason.

If someone can help me, i will be greatful.
Thanks for advance ;-)

Re: Watchdog configuration in MKMxxZxxACxx5RM

MarMi — Wed, 26 Oct 2016 08:26:41 GMT

Hello David,

the configuration structure you use WDOG_MODULE_NORMAL_STOP_DI_CONFIG doesn't set WDOG_STCTRLH[DBGEN] and hence watchdog counter doesn't increment after device enters debug mode. Please modify this structure to see impact...

Note also that the latest drivers 4.1.5 provides more default watchdog configurations including one with watchdog counter enabled by default in debug mode WDOG_MODULE_NORMAL_STOP_DI_DBG_EN_CONFIG. I have tried your code with new structures:

void main (void) { SIM_Init (SIM_MODULE_ALL_PERIPH_ON_CONFIG); SIM_SetClkMode (SYSCLK_MODE0); SIM_SetClkDiv (SYSCLK_DIV1); FLL_Init (FLL_MODULE_FEI_20_25MHZ_CONFIG); WDOG_Init(WDOG_MODULE_NORMAL_STOP_DI_DBG_EN_CONFIG(WDOG_LPO_CLK,WDOG_DIV1,1500));

// WDOG_Init(WDOG_MODULE_NORMAL_STOP_DI_DBG_DI_CONFIG(WDOG_LPO_CLK,WDOG_DIV1,1500));

while(1); }

When placing breakpoint on SIM_Init ... source line in IAR EWARM device execution stops at this line periodically notifying a system reset caused by the watchdog timer overflow. It works regardless whether DBG_EN or DBG_DI configuration is used. However, if you step through the code or put breakpoint on while(1); source line then second configuration DBG_DI will not work because device is in debug mode for the most of the time.

Kind regards,

Martin M.

Re: Watchdog configuration in MKMxxZxxACxx5RM

dmartinez1 — Fri, 28 Oct 2016 13:43:15 GMT

I really set all configurations of the library not only the configuration that i mentioned previously, as well as all this i did it using the console as help. I have used the last library following your advice, but i got the same result. :-(

Re: Watchdog configuration in MKMxxZxxACxx5RM

MarMi — Fri, 28 Oct 2016 14:02:06 GMT

Hello David,

are you using your own board or TWR KM34Z128? What toolchain do you use? I will try running example at the same conditions and send you project.

Kind regards,

Martin M.

Re: Watchdog configuration in MKMxxZxxACxx5RM

dmartinez1 — Fri, 28 Oct 2016 14:34:13 GMT

it's my own board, i am using kinetis. I really am starting the project so there just is the clock configuration

SIM_Init (SIM_MODULE_ALL_PERIPH_ON_CONFIG); SIM_SetClkMode (SYSCLK_MODE0); SIM_SetClkDiv (SYSCLK_DIV1); FLL_Init (FLL_MODULE_FEI_20_25MHZ_CONFIG);

Re: Watchdog configuration in MKMxxZxxACxx5RM

MarMi — Fri, 28 Oct 2016 14:51:46 GMT

Hi David,

do you have TWR board - can you try the same on TWR?

Martin M.

Re: Watchdog configuration in MKMxxZxxACxx5RM

dmartinez1 — Mon, 31 Oct 2016 11:15:34 GMT

Sorry, I don't have a TWR available

Re: Watchdog configuration in MKMxxZxxACxx5RM

MarMi — Tue, 01 Nov 2016 15:01:24 GMT

Hello David,

the reason could be missing low frequency external crystal (32.768 kHz) on your board. After device power up, the external clock is selected for clocking several peripherals including WDOG. Because crystal is not present some sub-blocks of WDOG are not clocked and therefore reset signal is not generated. The example below selects a low-power internal oscillator (1 kHz) instead of an external 32.726 kHz clock source for WDOG operation. I have tested this code on MKM14 sensor board (HW from DRM169) and watchdog has reset device as expected. Please try this code also on your board:

#include "drivers.h"

void main (void)
{
  SIM_Init (SIM_MODULE_ALL_PERIPH_ON_CONFIG);

  /* clock mode 1:1:1, 24MHz */
  SIM_SetClkMode (SYSCLK_MODE0);
  SIM_SetClkDiv (SYSCLK_DIV1);
  FLL_Init (FLL_MODULE_FEI_20_25MHZ_CONFIG);

  /* select 1 kHz LPO for watchdog sub-block operation */
  SIM_SelOsc32kClk (SIM_OSC32K_SRC4);

  /* Watchdog timeout is of 1.5 sec approximately */
  WDOG_Init(WDOG_MODULE_NORMAL_STOP_DI_DBG_DI_CONFIG(WDOG_LPO_CLK,WDOG_DIV1,1500));

  while(1);
}‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

Kind regards,

Martin M.

Re: Watchdog configuration in MKMxxZxxACxx5RM

dmartinez1 — Tue, 08 Nov 2016 10:10:20 GMT

Good Morning Martin,

i finally got to try my firmware on a TWR. Now i can say to you that the same firmware go well on the TWR but on my PCB not. is it possible that any configuracion hardware is different between them?

Kind regards,

David M.

Re: Watchdog configuration in MKMxxZxxACxx5RM

MarMi — Tue, 08 Nov 2016 11:46:13 GMT

#include "drivers.h"

void main (void)
{
  SIM_Init (SIM_MODULE_ALL_PERIPH_ON_CONFIG);

  /* clock mode 1:1:1, 24MHz */
  SIM_SetClkMode (SYSCLK_MODE0);
  SIM_SetClkDiv (SYSCLK_DIV1);
  FLL_Init (FLL_MODULE_FEI_20_25MHZ_CONFIG);

  /* select 1 kHz LPO for watchdog sub-block operation */
  SIM_SelOsc32kClk (SIM_OSC32K_SRC4);

  /* Watchdog timeout is of 1.5 sec approximately */
  WDOG_Init(WDOG_MODULE_NORMAL_STOP_DI_DBG_DI_CONFIG(WDOG_LPO_CLK,WDOG_DIV1,1500));

  while(1);
}‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

Hi David,

if you tried the code above on your board and it doesn't work then we need to review your board - please contact me @ martin.mienkina@nxp.com.

Note that macro that must be included in software on any MKMxx board without external 32.768 kHz crystal to allow watchdog initialization is:

SIM_SelOsc32kClk (SIM_OSC32K_SRC4);

Kind regards,

Martin M.