topic KL03 rtc clock instable in Kinetis Microcontrollers

KL03 rtc clock instable

Lupo — Mon, 22 Aug 2016 15:09:07 GMT

I have developed a project with a MKL03Z32VFG4 with a 32768Hz crystal and powered by a 2045 coin battery.

The application uses only the RTC seconds counter and in normal run mode the clock remains always precise and correct. The mcu enters in VLSS0 easily and current is under 1uA; but when it exits from low power state the clock counter is incorrect and the seconds count can be a lesser or higher, without any apparent reason.

All the prototypes ( >10) we have tested present this problem. Do someone have an idea of where to look, hw? fw?

Thanks for any suggestion...

Re: KL03 rtc clock instable

rastislav_pavlanin — Mon, 22 Aug 2016 15:33:31 GMT

Hi Michael,

I would recommend customer to check whether I/O pads (XTAL/EXTAL) are not in latched state as dedicated after recovery from VLLS mode. Check ACKISO definition in PMC module chapter.

regards

Re: KL03 rtc clock instable

Lupo — Mon, 22 Aug 2016 16:42:43 GMT

I am using KDS v3.2.0 and KSDK 1.3.0 with some PE components and in Events.c I have:

void LLWU_IRQHandler(void)

{

POWER_SYS_ClearAckIsolation();

POWER_SYS_ClearWakeupPinFlag(kPowerManagerWakeupPin4);

}

Is this not enough?

Re: KL03 rtc clock instable

rastislav_pavlanin — Tue, 23 Aug 2016 07:02:19 GMT

well, it could depend on in what time the function is executed.

NOTE:

For LLWU Flag X registers:

For LLS, this is the source causing the CPU interrupt flow. So, interrupt handler execution is expected.
For VLLS, this is the source causing the MCU reset flow

I would expect that for VLLS0 mode you detect whether the reset was caused by LLWU wake up trought the system reset status registers.

regards