Kinetis MicrocontrollersのトピックRe: setting interrupt priorities

setting interrupt priorities

akshaykatare — Wed, 17 Aug 2016 15:10:12 GMT

Hi,

I have following interrupts,

1)External interrupt at PORTA

2)LPTMR0

3)ADC0

4)PIT0

5)TPM1

6)TPM0

I have to set priorities as below written in brackets

1)External interrupt at PORTA (0)highest

2)LPTMR0 (1)

3)ADC0 (2)

4)PIT0 (3)

5)TPM1 (4)

6)TPM0 (5)lowest

I have read many documents, through that I got following information.

There is register NVIC_IPRx.

In that register, four sections of 8 bits are there. Each 8 bit section is for respective interrupt.

But out of that 8 bits, only highest 2 nibbles are available for writing . Then how can I set priority for respective interrupt greater than 3(as through two bits we can set values only up to 3) ?

Please let me know proper procedure for setting priorities as listed above.

Thanks and regards,

Akshay.

Re: setting interrupt priorities

BlackNight — Wed, 17 Aug 2016 16:14:59 GMT

Hi Akshay,

What microcontroller are you using? If you only have 2 bits implemented, then you have 0, 1, 2, 3 or four different priorities. No way to have more.

You might have a read at https://mcuoneclipse.com/2016/08/14/arm-cortex-m-interrupts-and-freertos-part-1/ .

I hope this helps,

Erich

Re: setting interrupt priorities

davidsherman — Wed, 17 Aug 2016 16:22:23 GMT

You didn't mention what part you are using, but if there are only 4 levels of interrupts available (2 bits), then a couple of those will have to share priorities. Nothing wrong with that, it just means if another interrupt of the same priority happens during the ISR for the first one, its ISR will run after the first one is finished.

Re: setting interrupt priorities

akshaykatare — Wed, 17 Aug 2016 18:09:40 GMT

Sorry i forgot to tell device.

using MKL17Z128VLH4 and core is mo+.

But in document written also that priority can assign 0-192.Then how can assign this with two bits?

Re: setting interrupt priorities

davidsherman — Wed, 17 Aug 2016 18:21:41 GMT

The ARM M0+ core is flexible, and the general specification allows for up to 192 priority levels depending on the implementation. The M0+ core implementation in this part only supports 4 priority levels.

Re: setting interrupt priorities

BlackNight — Thu, 18 Aug 2016 05:29:59 GMT

Hi Akshay,

there are not 0-192 priority levels. The ARM core would allow up to 127 *preemption* levels with up to 256 (8bit) interrupt values.

I recommend to have a read at https://mcuoneclipse.com/2016/08/14/arm-cortex-m-interrupts-and-freertos-part-1/, especially the section about the shifted interrupt interrupt bits. Because the NXP implementation of the Kinetis L series implements only 2 interrupt priority bits, there are 2^2 (4) interrupt priority levels: 0, 64, 128, 192. This is where your 0-192 is coming from, but you only can set these four values.

I hope this helps,

Erich

Re: setting interrupt priorities

akshaykatare — Sat, 20 Aug 2016 13:34:27 GMT

Hi,

As there are only four priorities.

I have set priority as follows,

for External interrupt at PORTA : NVIC_IPR7 |= 0x0000000

for LPTMR0 : NVIC_IPR7 |= 0x0000040

for ADC0 : NVIC_IPR3 |= 0x80000000

for PIT0 : NVIC_IPR5 |= 0x00C00000

for TPM1 :NVIC_IPR4 |= 0x00C00000

for TPM0 :NVIC_IPR4 |= 0x0000C000

I am assuming as follows,

External interrupt will have highest priority,

then LPTMR0, then ADC0, and finally remaining interrupts(PIT0, TPM1, YPM0) will have same and lowest priority.

means if ADC0 interrupt is in progress and LPTMR0 interrupt will occur, then ADC0 will become pending and LPTMR0 will become active

and after LPTMR0 interrupt get processed ADC0 interrupt will again come into picture.

Is my assumption is correct?

please let me know ASAP.

Re: setting interrupt priorities

akshaykatare — Sat, 20 Aug 2016 13:35:54 GMT

Hi,

As there are only four priorities.

I have set priority as follows,

for External interrupt at PORTA : NVIC_IPR7 |= 0x0000000

for LPTMR0 : NVIC_IPR7 |= 0x0000040

for ADC0 : NVIC_IPR3 |= 0x80000000

for PIT0 : NVIC_IPR5 |= 0x00C00000

for TPM1 :NVIC_IPR4 |= 0x00C00000

for TPM0 :NVIC_IPR4 |= 0x0000C000

I am assuming as follows,

External interrupt will have highest priority,

then LPTMR0, then ADC0, and finally remaining interrupts(PIT0, TPM1, YPM0) will have same and lowest priority.

means if ADC0 interrupt is in progress and LPTMR0 interrupt will occur, then ADC0 will become pending and LPTMR0 will become active

and after LPTMR0 interrupt get processed ADC0 interrupt will again come into picture.

Is my assumption is correct?

please let me know ASAP.