topic Re: MK20DN128VLH5 in Kinetis Microcontrollers

MK20DN128VLH5

senadtursic — Sat, 23 Jul 2016 03:11:09 GMT

Hello,

I am using MK20DN128VLH5 in my new design. I checked all available documents what I could find. I need more info about pins electrical specifications.

Do you have any document you could email to me? I have some unused pins as well and I need more info what would be the best way to do with them.

Best Regards

Senad

Re: MK20DN128VLH5

Robin_Shen — Tue, 26 Jul 2016 02:48:57 GMT

Hi Senad,

The pins electrical specifications can be found in the datasheet( K20P64M50SF0 ).

The documents of MK20DN128VLH5 are in this weblink.

About the usused pins, please refer the "5.2 Recommended connection for unused analog and digital pins" in K22P121M100SF9.

The K22 series is recommended for the new design. You can have a look at MK22FN128VLH10, it is cost effective.

Best Regards,

Robin

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Re: MK20DN128VLH5

senadtursic — Tue, 26 Jul 2016 15:08:31 GMT

Thanks Robin. This is really helpful.

Regards

Senad

Re: MK20DN128VLH5

senadtursic — Wed, 27 Jul 2016 17:44:16 GMT

Hi Robin,

I am not clear with those two pins, can you please help with this?:

VOUT33 , Tie to input, which input?

VREGIN, Tie to output, which output?

Regards

Senad

Re: MK20DN128VLH5

Robin_Shen — Thu, 28 Jul 2016 00:57:24 GMT

Hi Senad,

The input is VREGIN, and the output is VOUT33.

This means connect VREGIN and VOUT33 together and tie them to ground through a 10k resistor.

Best Regards,

Robin

Re: MK20DN128VLH5

senadtursic — Fri, 29 Jul 2016 16:16:03 GMT

Hi Robin,

I need more info about your recommendation for the new design. May I have your Email?

Best Regards

Senad

Re: MK20DN128VLH5

senadtursic — Mon, 01 Aug 2016 18:20:28 GMT

Hi Robin,

Why the K22 is recommended for the new design over the K20?

My plan is use the MK22FN128VLH10 as sound card. The i2S audio must be synchronized with the USB audio. Is this can be established with the K20/K22 chip?

Regards

Senad

Re: MK20DN128VLH5

Robin_Shen — Tue, 02 Aug 2016 06:47:29 GMT

MK22FN128VLH10:

100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

USB full-speed device crystal-less operation, it has internal 48MHz oscillator.(Cost Effective)

24KB SRAM, larger that 16KB( MK20DN128VLH5 )

Lower Budgetary Price excluding tax

Kinetis SDK supported.(If you have not used KSDK2.0, please read Introducing Kinetis SDK v2 first. You can download and install it refer the methods in How to: install KSDK 2.0.)

But the MK22FN128VLH10 don't have internal USB regulator(It doesn't have VREGIN and VOUT33, only have USBVDD pin), you need refer "3.9.1.2 USB Power Distribution" in K22P121M100SF9RM.

I am not sure: is this can be established with the K20/K22 chip? Maybe you can ask another question.

Robin

Re: MK20DN128VLH5

senadtursic — Wed, 10 Aug 2016 22:17:56 GMT

I want to receive USB audio data from the Host PC (at a rate of 1ms), and from USB audio data generate synchronized audio clock outputs (MCLK, SCLK, and Fs) that drive the audio CODECs and the DSP. The digital audio clocks should bee completely synchronized (or locked) with the USB audio data from the Host PC.

I try to see can I get synchronized USB audio clock (locked) from the host (PC) as master to I2S without adding any extra PLL circuitry.

My frame rate is 48 kHz and MCLK is 24.576 MHz.

Regards

Senad

Re: MK20DN128VLH5

egoodii — Wed, 10 Aug 2016 23:36:56 GMT

AFAIK all USB audio endpoints implement the asynchronous data-rate form, in which the endpoint gives feedback to pace the host's sending to match the rate actually running at the CoDec. However, there is a definition for 'synchronous audio' in the USB spec, and that requires you to create an MCLK that is a 'clean multiple' of the USB frame-rate so that the CoDec datarate will exactly match. I am just starting a 'similar' process for industrial data, and plan on using an Si5351A-B-GT from Silicon Labs as the highly programmable frequency synthesizer. The CPU will need to maintain the frequency-lock function by watching sample-buffer run-out. There is no way to create an MCLK that is 'locked' to the host's actual crystal timing, AND to track it +/-100ppm as it drifts, without some kind of PLL.

Re: MK20DN128VLH5

senadtursic — Thu, 11 Aug 2016 04:12:09 GMT

Thanks.I assumed that could be a problem.