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    <title>topic Re: MK64FN1M0VLL12 Reference Manual in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK64FN1M0VLL12-Reference-Manual/m-p/505143#M31689</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi shaul dorf,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Actually, if the chip using the same reference manual ,then the register configuration is the same.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="84.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/53401i516A91F3C1560138/image-size/large?v=v2&amp;amp;px=999" role="button" title="84.jpg" alt="84.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; From the above picture, you will get that MK64FN1M0VLL12 should refer to this document, the reference manual which you are referring is correct.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; If you want to choose the MUX, and don't know which alternative chip-specific mean, please refer to page 246, 10.3.1 K64 Signal Multiplexing and Pin Assignments, here you will get the detail ALTn function.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="85.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/53440i7602F44148D8875B/image-size/large?v=v2&amp;amp;px=999" role="button" title="85.jpg" alt="85.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Wish it helps you!&lt;/P&gt;&lt;P&gt;Have a great day,&lt;/P&gt;&lt;P&gt;Jingjing&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 21 Jan 2016 03:28:07 GMT</pubDate>
    <dc:creator>kerryzhou</dc:creator>
    <dc:date>2016-01-21T03:28:07Z</dc:date>
    <item>
      <title>MK64FN1M0VLL12 Reference Manual</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK64FN1M0VLL12-Reference-Manual/m-p/505142#M31688</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="line-height: 115%; font-family: 'Arial','sans-serif'; font-size: 14pt; mso-ascii-theme-font: minor-bidi; mso-hansi-theme-font: minor-bidi; mso-bidi-font-family: Arial; mso-bidi-theme-font: minor-bidi;"&gt;&lt;STRONG&gt;FRDM-K64F&lt;/STRONG&gt; uses &lt;/SPAN&gt;&lt;SPAN style="line-height: 115%; font-family: 'Arial','sans-serif'; font-size: 14pt; mso-ascii-theme-font: minor-bidi; mso-hansi-theme-font: minor-bidi; mso-bidi-font-family: Arial; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: HelveticaLTStd-Roman;"&gt;&lt;STRONG&gt;MK64FN1M0VLL12 &lt;/STRONG&gt;processor.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="line-height: 115%; font-family: 'Arial','sans-serif'; font-size: 14pt; mso-ascii-theme-font: minor-bidi; mso-hansi-theme-font: minor-bidi; mso-bidi-font-family: Arial; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: HelveticaLTStd-Roman;"&gt;In reference manual different register configurations referee to chip-specific configuration. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="line-height: 115%; font-family: 'Arial','sans-serif'; font-size: 14pt; mso-ascii-theme-font: minor-bidi; mso-hansi-theme-font: minor-bidi; mso-bidi-font-family: Arial; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: HelveticaLTStd-Roman;"&gt;For example PORTx PCRn (page 283)&amp;nbsp; in K64 Sub-Family Reference Manual&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="line-height: 115%; font-family: 'Arial','sans-serif'; font-size: 14pt; mso-ascii-theme-font: minor-bidi; mso-hansi-theme-font: minor-bidi; mso-bidi-font-family: Arial; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: HelveticaLTStd-Roman;"&gt;Document Number: K64P144M120SF5RM Rev. 2,&lt;BR /&gt;January 2014&lt;/SPAN&gt; &lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="ReferencManual.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/54126i9B65740069754D0A/image-size/large?v=v2&amp;amp;px=999" role="button" title="ReferencManual.jpg" alt="ReferencManual.jpg" /&gt;&lt;/span&gt;&lt;BR /&gt; &lt;SPAN style="line-height: 115%; font-family: 'Arial','sans-serif'; font-size: 14pt; mso-ascii-theme-font: minor-bidi; mso-hansi-theme-font: minor-bidi; mso-bidi-font-family: Arial; mso-bidi-theme-font: minor-bidi;"&gt;Where this chip-specific can be found and downloaded ?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 20 Jan 2016 20:29:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK64FN1M0VLL12-Reference-Manual/m-p/505142#M31688</guid>
      <dc:creator>shauldorf</dc:creator>
      <dc:date>2016-01-20T20:29:47Z</dc:date>
    </item>
    <item>
      <title>Re: MK64FN1M0VLL12 Reference Manual</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK64FN1M0VLL12-Reference-Manual/m-p/505143#M31689</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi shaul dorf,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Actually, if the chip using the same reference manual ,then the register configuration is the same.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="84.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/53401i516A91F3C1560138/image-size/large?v=v2&amp;amp;px=999" role="button" title="84.jpg" alt="84.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; From the above picture, you will get that MK64FN1M0VLL12 should refer to this document, the reference manual which you are referring is correct.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; If you want to choose the MUX, and don't know which alternative chip-specific mean, please refer to page 246, 10.3.1 K64 Signal Multiplexing and Pin Assignments, here you will get the detail ALTn function.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="85.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/53440i7602F44148D8875B/image-size/large?v=v2&amp;amp;px=999" role="button" title="85.jpg" alt="85.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Wish it helps you!&lt;/P&gt;&lt;P&gt;Have a great day,&lt;/P&gt;&lt;P&gt;Jingjing&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 21 Jan 2016 03:28:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/MK64FN1M0VLL12-Reference-Manual/m-p/505143#M31689</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2016-01-21T03:28:07Z</dc:date>
    </item>
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