<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>Kinetis MicrocontrollersのトピックRe: K64 External SRAM Question</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/K64-External-SRAM-Question/m-p/503618#M31604</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For the external SRAM is using Flexbus connected, please check the FB_CSMRn [BAM] bits setting.&lt;/P&gt;&lt;P&gt;For the external SRAM memory size is 1M Byte, the FB_CSMRn[BAM] bits value should be 0xF.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The Flexbus clock is using bus clock, which need to use 4 cycles to read 16/32 bit data.&lt;/P&gt;&lt;P&gt;If the external SRAM memory supports burst access, customer could set Flexbus to start burst transfer, which could enhance the external SRAM access speed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Wish it helps.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;best regards,&lt;/P&gt;&lt;P&gt;Ma Hui&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 24 Dec 2015 05:14:23 GMT</pubDate>
    <dc:creator>Hui_Ma</dc:creator>
    <dc:date>2015-12-24T05:14:23Z</dc:date>
    <item>
      <title>K64 External SRAM Question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/K64-External-SRAM-Question/m-p/503617#M31603</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Everyone, I am now using K64 as CPU core of my board. I Use an External SRAM (IS61LV51216) which have a size of 1M Byte as a supplement space of my board. However, I encountered a question&amp;nbsp; when I want to access upper 512k of the chip. I Map the whole 1M address to my internal address( 0x70000000-0x701000000). I can't access the address greater than 0x7008000. When I change the map address to( 0x70080000-0x701800000) , I can access the address(0x70080000-0x701000000) and can't access the remaining? Is there has any method to map to 1M external space?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; There, I have another question. Does the access speed of internal sram and external sram has great difference? When I use internal sram as my calculate variable,occupancy rate of cpu is 41%, which change to 97% when I defined my varible to external. Is there has any method to promote the external sram access speed?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Dec 2015 13:45:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/K64-External-SRAM-Question/m-p/503617#M31603</guid>
      <dc:creator>cuizhuangping</dc:creator>
      <dc:date>2015-12-23T13:45:13Z</dc:date>
    </item>
    <item>
      <title>Re: K64 External SRAM Question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/K64-External-SRAM-Question/m-p/503618#M31604</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For the external SRAM is using Flexbus connected, please check the FB_CSMRn [BAM] bits setting.&lt;/P&gt;&lt;P&gt;For the external SRAM memory size is 1M Byte, the FB_CSMRn[BAM] bits value should be 0xF.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The Flexbus clock is using bus clock, which need to use 4 cycles to read 16/32 bit data.&lt;/P&gt;&lt;P&gt;If the external SRAM memory supports burst access, customer could set Flexbus to start burst transfer, which could enhance the external SRAM access speed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Wish it helps.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;best regards,&lt;/P&gt;&lt;P&gt;Ma Hui&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 24 Dec 2015 05:14:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/K64-External-SRAM-Question/m-p/503618#M31604</guid>
      <dc:creator>Hui_Ma</dc:creator>
      <dc:date>2015-12-24T05:14:23Z</dc:date>
    </item>
  </channel>
</rss>

