Kinetis MicrocontrollersのトピックRe: Configure OSC1 as EXTAL ref for PLL0 and PLL1

Configure OSC1 as EXTAL ref for PLL0 and PLL1

rameshgoud — Tue, 19 Jan 2016 13:31:19 GMT

Hi,

Am using 12 Mhz crystal as my External reference clock which is OSC1 and another high range crystal is using as OSC0, I want the configurations for PLL0 and PLL1 which are using the EXTAL as OSC1 only.

Here am sharing my code snippet for configuring MCG and DDR

MCG:

/* Generate a reset request on a loss of OSC1 external reference clock and High frequency range selected for the crystal oscillator */

temp8 = ESAL_GE_MEM_READ8(MCG_C10);

temp8 &= ~(0x30 | 0x8 | 0x4);

temp8 |= (1<<4 | 0 << 3 | 0 << 2);

ESAL_GE_MEM_WRITE8(MCG_C10, temp8);

/* External reference clock is selected and write frdiv (5) value */

temp8 = ESAL_GE_MEM_READ8(MCG_C1);

temp8 &= ~(0x4 | 0x38 | 0xc0);

temp8 = 2<<6 | frdiv<<3;

ESAL_GE_MEM_WRITE8(MCG_C1, temp8);

/* Wait until clock is stable */

for(temp32=0;temp32<100000;temp32++);

/* FBE Mode */

/* External clock monitor is disabled for OSC1 */

ESAL_GE_MEM_WRITE8(MCG_C12, ESAL_GE_MEM_READ8(MCG_C12) | MCG_C12_CME); ( MCG_C12_CME => 0x20 )

/* PLL0, OSC1 is selected as the reference clock */

ESAL_GE_MEM_WRITE8(MCG_C5, ESAL_GE_MEM_READ8(MCG_C5) | (MCG_C5_PLLREFSEL)); ( MCG_C5_PLLREFSEL => 0x80 )

/* Select PLL0 as the source of the PLLS mux (PLLCS filed) */

ESAL_GE_MEM_WRITE8(MCG_C11, ESAL_GE_MEM_READ8(MCG_C11) & (~MCG_C11_PLLCS)); (MCG_C11_PLLCS => 0x10 )

/* Set PRDIV0 value */

temp8 = ESAL_GE_MEM_READ8(MCG_C5);

temp8 &= ~MCG_C5_PRDIV;

temp8 |= (prdiv_val - 1);

ESAL_GE_MEM_WRITE8(MCG_C5, temp8);

/* Set PLLS bit and VDIV0 values */

temp8 = ESAL_GE_MEM_READ8(MCG_C6);

temp8 &= ~MCG_C6_VDIV;

temp8 |= MCG_C6_PLLS | (vdiv_val - 16);

ESAL_GE_MEM_WRITE8(MCG_C6, temp8);

/* Wait for PLLST status bit to set */

for(temp32=0;temp32<100000;temp32++);

/* PBE Mode */

/* Output of FLL or PLLCS is selected (depends on PLLS control bit) */

ESAL_GE_MEM_WRITE8(MCG_C1, ESAL_GE_MEM_READ8(MCG_C1) & (~MCG_C1_CLKS)); ( MCG_C1_CLKS => 0xc0 )

/* Wait for clock status bits to update */

for(temp32=0;temp32<100000;temp32++);

DDR:

ESAL_GE_MEM_WRITE8(MCG_C11, ESAL_GE_MEM_READ8(MCG_C11) | (MCG_C11_PLLREFSEL2)); (MCG_C11_PLLREFSEL2 => 0x80)

/* Set PRDIV1 value */

temp8 = ESAL_GE_MEM_READ8(MCG_C11);

temp8 &= ~MCG_C11_PRDIV1; (MCG_C11_PRDIV1 => 7)

temp8 |= (prdiv_val - 1); (prdiv_val => 5)

ESAL_GE_MEM_WRITE8(MCG_C11, temp8);

/* Set VDIV1 value (Divide Factor is 30-16 = 14) */

temp8 = ESAL_GE_MEM_READ8(MCG_C12);

temp8 &= ~MCG_C12_VDIV1; ( MCG_C12_VDIV1 => 0x1F)

temp8 |= (vdiv_val - 16); (vdiv_val => 30)

ESAL_GE_MEM_WRITE8(MCG_C12, temp8);

/* Now enable the PLL clock */

ESAL_GE_MEM_WRITE8(MCG_C11, ESAL_GE_MEM_READ8(MCG_C11) | (MCG_C11_PLLCLKEN2)); (MCG_C11_PLLCLKEN2 => 0x40 )

/* Wait for LOCK bit to set */

for(temp32=0;temp32<100000;temp32++);

when i configure the Register MCG_C12 to enable the clock monitor for OSC1, It's throwing the error as unable to read the RAM.

help me on the above...

Re: Configure OSC1 as EXTAL ref for PLL0 and PLL1

kerryzhou — Wed, 20 Jan 2016 06:13:20 GMT

Hi Ramesh Goud,

About this question, we have some similar questions in our community, please refer to these post:

Need help setting up MCG on K60 With Ext Osc1

Re: Kinetis K60 oscillator selection

Wish it helps you!

If you still have question, please contact with me!

Have a great day,

Jingjing

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

Re: Configure OSC1 as EXTAL ref for PLL0 and PLL1

rameshgoud — Thu, 21 Jan 2016 09:08:43 GMT

Hi Zhou,

I agree with you, i need the Register configuration settings to pass FEI, FBE and PBE modes and the RTC OSC as Source instead of OSC0.

please respond for the same

Thanks in advance

Re: Configure OSC1 as EXTAL ref for PLL0 and PLL1

kerryzhou — Thu, 28 Jan 2016 06:22:21 GMT

Hi Ramesh Goud,

Sorry for my later reply!

You can refer to this initialization code:

void __pe_initialize_hardware(void)
{
    volatile int counter = 500;
  /*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/
  /*** ### MK70FN1M0VMJ12 "Cpu" init code ... ***/
  /*** PE initialization code after reset ***/
  /* SIM_SCGC6: RTC=1 */
  SIM_SCGC6 |= (uint32_t)0x20000000UL;
  if ((RTC_CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */
    /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
    RTC_CR &= (uint32_t)~0x3C00UL;
    /* RTC_CR: OSCE=1 */
    RTC_CR |= (uint32_t)0x0100UL;
    /* RTC_CR: CLKO=0 */
    RTC_CR &= (uint32_t)~0x0200UL;
  }
  /* System clock initialization */
  /* SIM_SCGC5: PORTE=1,PORTC=1,PORTA=1 */
  SIM_SCGC5 |= (uint32_t)0x2A00UL;     /* Enable clock gate for ports to enable pin routing */
  if ( *((uint8_t*) 0x03FFU) != 0xFFU) {
    MCG_C3 = *((uint8_t*) 0x03FFU);
    MCG_C4 = (MCG_C4 & 0xE0U) | ((*((uint8_t*) 0x03FEU)) & 0x1FU);
  }
  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=2,OUTDIV4=5,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SIM_CLKDIV1 = (uint32_t)0x01250000UL; /* Update system prescalers */
  /* SIM_CLKDIV4: NFCDIV=7 */
  SIM_CLKDIV4 |=  SIM_CLKDIV4_NFCDIV(7);
  /* SIM_SOPT2: PLLFLLSEL=1 */
   SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~0x00020000UL) | (uint32_t)0x00010000UL); /* Lior Select PLL 0 as a clock source for various peripherals */     //Hui's addition (remark)
 //SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~0x00020000UL) | (uint32_t)0x00020000UL); /* Select PLL 1 as a clock source for various peripherals */       //Hui's addition
  /* SIM_SOPT1: OSC32KSEL=1 */
  SIM_SOPT1 |= (uint32_t)0x00080000UL; /* RTC oscillator drives 32 kHz clock for various peripherals */
  /* SIM_SCGC1: OSC1=1 */
  SIM_SCGC1 |= (uint32_t)0x20UL;
  /* PORTA_PCR18: ISF=0,MUX=0 */
  PORTA_PCR18 &= (uint32_t)~0x01000700UL;
  /* PORTE_PCR24: ISF=0,MUX=0 */
  PORTE_PCR24 &= (uint32_t)~0x01000700UL;
  /* PORTE_PCR25: ISF=0,MUX=0 */
  PORTE_PCR25 &= (uint32_t)~0x01000700UL;
  /* Switch to FBE Mode */
  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
  OSC0_CR =  (uint8_t)0x80U; //(uint8_t)0x80U; //temporary for testing ONLY !!!!!!!!!!!!!!!!!!!!!!!!!!!!
  /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
  OSC1_CR = (uint8_t)0xA0U; //origin 0x80U
  /* MCG_C7: OSCSEL=0 */
  MCG_C7 |= (uint8_t)0x01U; //origin MCG_C7 &= (uint8_t)~(uint8_t)0x01U;
  /* MCG_C10: LOCRE2=0,??=0,RANGE1=2,HGO1=1,EREFS1=1,??=0,??=0 */
  MCG_C10 = (uint8_t)0x1CU; //origin 0x2CU
  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
  MCG_C2 = (uint8_t)0x20U; //origin 0x21U;
  /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
  MCG_C1 = (uint8_t)0xA8U;
  /* MCG_C4: DMX32=0,DRST_DRS=0 */
  MCG_C4 &= (uint8_t)~(uint8_t)0xE0U;
  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=4 */
  MCG_C5 = (uint8_t)0xC0U; //origin 0x04U;
  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */
  MCG_C6 = (uint8_t)0x04U; //origin 0x08U
  /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=3 */
  //MCG_C11 = (uint8_t)0x03U;
  /* MCG_C11: PLLCLKEN1=1 */
  MCG_C11 = (uint8_t)0xC0;            /* Enable the PLL */ //origin 0x40U;
  /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=8 */
  //MCG_C12 = (uint8_t)0x08U; //origin - is open
    while(counter)
    {
        counter--;
    }
  while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
  }
  while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
  }
   MCG_C6 |= 0x40;        //Change#8 //origin - doesn't exist
   MCG_C12 = 0x09;       //Change#9  //origin - doesn't exist
  /* Switch to PBE Mode */
  /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */
  //MCG_C6 = (uint8_t)0x48U;  //origin - is open
  while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
  }
  while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL0 locked */            //Change#11 (remark)
  }
  while((MCG_S2 & MCG_S2_LOCK1_MASK) == 0x00U) { /* Wait until PLL1 locked */           //Change#12 //origin - doesn't exist
  }
  /* Switch to PEE Mode */
  /* MCG_C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
  MCG_C1 = (uint8_t)0x28U;
  while((MCG_S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
  }
  /* MCG_C6: CME0=1 */
  //MCG_C6 |= (uint8_t)0x20U;            /* Enable the clock monitor */  //origin - is open
  /*** End of PE initialization code after reset ***/
  /*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/
}

This code can pass the PBE and PEE modes with the RTC OSC as the source.

Wish it helps you!

If you still have question, please contact with me!

Have a great day,

Jingjing

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

Re: Configure OSC1 as EXTAL ref for PLL0 and PLL1

rameshgoud — Thu, 04 Feb 2016 14:18:45 GMT

Hi Jing,

Thanks for the reply,

I tried with the same on k70, the RTC crystal (32.767KHz) as the primary oscillator, hence it impacts on the system performance, i.e. for Hardware initialization it's taking more than 2 mins.

As I said earlier we are working with Nucleus OS, and initially it'll configured the registers from .XML.

Please help me how to overcome this issue and suggest me if I use the RTC crystal as primary Oscillator.

Thanks in Advance,

Ramesh

Re: Configure OSC1 as EXTAL ref for PLL0 and PLL1

kerryzhou — Fri, 05 Feb 2016 02:11:25 GMT

Hi Ramesh ,

Do you mean this function which I give you :void __pe_initialize_hardware(void) take more than 2 minutes? I already check it, this function time couldn't caused 2 minutes, did you use the 32.768K as the core and process some other code before?

I suggest you use __pe_initialize_hardware function directly after the MCU power on, don't do other codes, after the clock mode transfer to PEE and select the OSC clock, the core clock should be higher ,then do the function which you need.

Wish it helps you!

If you still have question, please contact with me!

Have a great day,

Jingjing

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------