CPU Not Halting with J-Link Debugger

dspNeil — Thu, 09 Feb 2012 10:12:29 GMT

I'm using a Kwikstik as my debugger on my custom K53DN512 board. I have been debugging successfuly for several weeks, but yesterday I somehow locked a chip, and today, I am getting a message that J-Link can no longer halt the device after reset. Has anybody seen this? I have tried switching between JTAG and SWD with no success. Please help! Here's the output from the J-Link Commander software when issuing a reset. SWD results are similar:

SEGGER J-Link Commander V4.40b ('?' for help)

Compiled Dec 22 2011 10:55:05

DLL version V4.40b, compiled Dec 22 2011 10:54:45

Firmware: J-Link Lite-FSL V1 compiled Jan 31 2011 11:00:51

Hardware: V1.00

S/N: 430110131

VTarget = 3.435V

Info: TotalIRLen = 4, IRPrint = 0x01

Info: Found Cortex-M4 r0p0, Little endian.

Info: TPIU fitted.

Info: ETM fitted.

Info: ETB present.

Info: CSTF present.

Info: FPUnit: 6 code (BP) slots and 2 literal slots

Found 1 JTAG device, Total IRLen = 4:

#0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)

Cortex-M4 identified.

JTAG speed: 100 kHz

J-Link>r

Reset delay: 0 ms

Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.

Info: TotalIRLen = 4, IRPrint = 0x01

Info: Found Cortex-M4 r0p0, Little endian.

Info: TPIU fitted.

Info: ETM fitted.

Info: ETB present.

Info: CSTF present.

Info: FPUnit: 6 code (BP) slots and 2 literal slots

Info: Found Cortex-M4 r0p0, Little endian.

Info: TPIU fitted.

Info: ETM fitted.

Info: ETB present.

Info: CSTF present.

Info: FPUnit: 6 code (BP) slots and 2 literal slots

WARNING: S_RESET_ST not cleared

WARNING: CPU did not halt after reset.

Info: Found Cortex-M4 r0p0, Little endian.

Info: TPIU fitted.

Info: ETM fitted.

Info: ETB present.

Info: CSTF present.

Info: FPUnit: 6 code (BP) slots and 2 literal slots

WARNING: CPU could not be halted

Info: Core did not halt after reset, trying to disable WDT.

WARNING: CPU did not halt after reset.

Info: Found Cortex-M4 r0p0, Little endian.

Info: TPIU fitted.

Info: ETM fitted.

Info: ETB present.

Info: CSTF present.

Info: FPUnit: 6 code (BP) slots and 2 literal slots

WARNING: CPU could not be halted

WARNING: CPU did not halt after reset.

Info: Found Cortex-M4 r0p0, Little endian.

Info: TPIU fitted.

Info: ETM fitted.

Info: ETB present.

Info: CSTF present.

Info: FPUnit: 6 code (BP) slots and 2 literal slots

WARNING: CPU could not be halted

WARNING: S_RESET_ST not cleared

Re: CPU Not Halting with J-Link Debugger

dspNeil — Fri, 10 Feb 2012 08:56:08 GMT

I believe that we figured out the issue. The Kwikstik has a 1k resistor (R113) between the MCU reset pin on the JTAG connector and the Kwikstik's Kinetis 3.3V supply. It appears that when the Kwikstik is used as a debugger for an external MCU, this 1k resistor acts as a pull-down, biasing the reset line low. It looks like sometimes the line would reset successfully, and sometimes it wouldn't. Pulling R113 seems to fix the issue.

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