Kinetis MicrocontrollersのトピックRe: SRAM retention over system reset

SRAM retention over system reset

iainrist — Wed, 03 Feb 2016 14:38:13 GMT

I am really only interested in SRAM retention over a software reset, but I thought this post could be a catch-all.

I am working on a Kinetic K10. I want to reset the microcontroller and retain some data over the reset. I realise I can use the System Register File to achieve this, since this is only reset via a power-on reset, but I am interested in other methods as well.

I did not see in the reference manual any mention in what state the SRAM comes up in after POR or the effect of the various system reset sources on the current state of the SRAM.

Does the SRAM come up filled with a static value after a power-on reset?

Does the SRAM retain its contents any/some/all system resets?

The K10 has multiple system reset sources. If the SRAM is retained over only some system resets, please could you indicate which ones.

Power-on reset

External pin reset

Low-voltage detect

Watchdog timer

Low leakage wakeup

Loss-of-clock (external)

Loss-of-clock (PLL)

Stop mode acknowledgement error

Software reset

Lockup reset

EzPort reset

MDM-AP system reset request

Re: SRAM retention over system reset

DavidS — Wed, 03 Feb 2016 15:17:12 GMT

Hi Iain,

Quick non in depth answer.

The SRAM retains its contents during non-POR resets.

I haven't tried each of your cases but as long as power is retained the SRAM contents are retained.

So if a low power or brown out occurs, SRAM not retained.

Maybe others have done some of your test cases and will reply too.

Regards,

David

Re: SRAM retention over system reset

iainrist — Wed, 03 Feb 2016 15:35:28 GMT

David,

Thanks. Pretty much as I wished/expected.

Any idea on the state of the SRAM after POR?

Iain

Re: SRAM retention over system reset

DavidS — Wed, 03 Feb 2016 16:12:39 GMT

Hi Iain,

SRAM after POR is not defined so could be anything.

Regards,

David

Re: SRAM retention over system reset

Jorge_Gonzalez — Thu, 04 Feb 2016 01:47:57 GMT

Hello Iain Rist:

Just to complement on David's response. For a Low leakage wakeup reset, if the device was in VLLS1 or VLLS0 power modes, then SRAM memory is powered off and so the contents are not retained.

Regards!

Jorge Gonzalez