topic Re: Freescale MK10DN512ZVLL10 ADC module/Peripheral conversions slowing down after 30-90 days and subsequently stalling/damaged permanently. in Kinetis Microcontrollers

Freescale MK10DN512ZVLL10 ADC module/Peripheral conversions slowing down after 30-90 days and subsequently stalling/damaged permanently.

titan99bijou — Mon, 14 Dec 2015 08:36:45 GMT

Chip: Freescale MK10DN512ZVLL10-4N30D (Kinetis K10)

Issue: ADC module/Peripheral conversions slowing down after 30-90 days and subsequently stalling/damaged permanently.

No of chips affected/damaged: 20 Nos.

Core Clock: 100Mhz

Bus Clock: 50MHz

ADC Operating Frequency: 50/8=6.25MHz

Hardware Average: No/Disabled

Long Sample: Yes

Long Sample clocks: Extra cycles

Total ADCs connected: 11

No. of Differential channels connected: 4

ADC Resolution :16-bit

No. of Single-ended channels connected: 7

ADC Resolution :16-bit

In-depth Problem:

The chip ADC module works as designed/engineered/coded in our production line & factory testing.
Once the chip is working in real-world application(industrial data aquisition), its works fine for atleast 30 days.
The trouble starts anywhere between 30-90 days where the ADC conversions really slows down & ultimately freezes.
Henceforth the aforementioned Chip-ADC module absolutely doesnt work on any valid ADC input signal.
Once the ADC clock is lowered or increased in code & reflashed, the ADC module reworks but just for a day or two.
Basically dead for future ADC conversions.
The code also uses FTM that is derived from Bus clock.It works absolutely perfect.
Rest all of the chip modules work as expected.
No heating or physical damage observed or loose solder contacts.
The VREF & VVA are shorted=3.3V same as the supply of the chip.
The VREFH & VREFL voltages are steady & corresponding pins in place.
No. of chips failed in this fashion ~20 Nos at different geolocations.

Attached is the Code* for Core clock, ADC clock & ADC reading.

Also attached is the schematic* for reference.

*Only ADC section.other details/specifics taken out

Please acknowledge, analyze, diagnose & suggest what is going wrong/what is causing ADC to damage/any corrections in code or schematic.Any suggestions will be appreciated.

Brij

Re: Freescale MK10DN512ZVLL10 ADC module/Peripheral conversions slowing down after 30-90 days and subsequently stalling/damaged permanently.

xiangjun_rong — Wed, 16 Dec 2015 08:57:43 GMT

From your phenomenon, it is difficult to get the root cause. But I have checked your code, it seems that your code has issue.

For example:

LDR R0,=SIM_BASE

LDR R1,[R0,#SIM_SCGC6_OFS]

MOV R2,#(1<<27)

ORR R1,R1,R2

STR R1,[R0,#SIM_SCGC6_OFS]

I do not think that the "MOV R2,#(1<<27)" is correct, as you know that the immediate value should less than 16 bits for MOV instruction so that the MOV can generate 32 bits coding. I have use the CW to compile the instruction, I get error for the above instruction. I think your assembly compiler has issue, can you tell me the assembly compiler you are using?

If you do want to use assembly language to develop code, can you switch to CW tools?

Xiangjun rong

Re: Freescale MK10DN512ZVLL10 ADC module/Peripheral conversions slowing down after 30-90 days and subsequently stalling/damaged permanently.

egoodii — Wed, 16 Dec 2015 19:12:56 GMT

Actually, the Cortex M4 instructions allow for 'somewhat more general' fixed values in addition to 'immediate 16 bits'.

From DUI0553A_cortex_m4_dgug.pdf:

Constant

You specify an Operand2 constant in the form:

#constant

where constant can be these (or for MVN [move negate] their inverse):

• any constant that can be produced by shifting an 8-bit value left by any number of bits

within a 32-bit word

• any constant of the form 0x00XY00XY

• any constant of the form 0xXY00XY00

• any constant of the form 0xXYXYXYXY.

How individual assemblers create the syntax to implement these different forms is probably 'implementation dependent'.

Re: Freescale MK10DN512ZVLL10 ADC module/Peripheral conversions slowing down after 30-90 days and subsequently stalling/damaged permanently.

titan99bijou — Thu, 17 Dec 2015 10:51:56 GMT

Hi Rong,

Thanks for your views & time spent there. But seems the instruction is behaving as desired. Am using a Keil 4 Assembler & attached is the snapshot of the debugger at that instruction.It can been seen that the MOV R2,#(1<<27) shifts 1, 27 bits to the Left thereby activating the ADC clock.

Can some1 please check my Core,Bus & ADC Clocks are in range & within specifications?

Re: Freescale MK10DN512ZVLL10 ADC module/Peripheral conversions slowing down after 30-90 days and s

sdw3kor — Sat, 05 Sep 2020 05:24:18 GMT

@titan99bijou did you get the solution or root cause of the problem ? I also have the similar issue and not getting any clue even with failure analysis by NXP.