topic Re: With 120MHz core clock (system clock) on MKV31F512VLL12, what is the maximum SPI clock i can generate and operate at? Please help on this question. in Kinetis Microcontrollers

With 120MHz core clock (system clock) on MKV31F512VLL12, what is the maximum SPI clock i can generate and operate at? Please help on this question.

sangameshvandal — Mon, 16 May 2016 20:07:42 GMT

With 120MHz core clock (system clock) on MKV31F512VLL12, can i generate SPI clock of 30MHz?

Re: With 120MHz core clock (system clock) on MKV31F512VLL12, what is the maximum SPI clock i can generate and operate at? Please help on this question.

egoodii — Tue, 17 May 2016 02:17:32 GMT

Yes. Max BusClock of 60MHz, and:

3.9.1.2 SPI clocking

The SPI module is clocked by the internal bus clock (the DSPI refers to it as system

clock). The module has an internal divider, with a minimum divide is two. So, the SPI

can run at a maximum frequency of bus clock/2.

Re: With 120MHz core clock (system clock) on MKV31F512VLL12, what is the maximum SPI clock i can generate and operate at? Please help on this question.

kerryzhou — Tue, 17 May 2016 03:19:02 GMT

Hi Sangamesh,

From the datasheet, you can get that, the SPI max baud is 30Mhz, If you using 120Mhz, your bus is 60Mhz.

As you know, the DBR, PBR, and BR fields in the CTARs select the frequency of SCK by the formula in the BR field description.

Then, you can choose, PBR=0, BR=0, DBR=1, you will get SPI clock = ((60Mhz/2)/2)*2=30Mhz.

Wish it helps you!

If you still have question, please contact me!
Have a great day,
Jingjing

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Re: With 120MHz core clock (system clock) on MKV31F512VLL12, what is the maximum SPI clock i can generate and operate at? Please help on this question.

sangameshvandal — Wed, 18 May 2016 17:11:37 GMT

Hi Jingjing

Thanks for the reply,

Let me explain you my scenario, MKV31F512VLL12 is communicating with a display (FTDI chip FT8XX) over SPI

With PBR=0, BR=0, DBR=0 (clock of 15MHz) communication works fine.

However with PBR=0, BR=0, DBR=1 (Theoretically clock of 30MHz) communication fails.

Note: FT8XX device supports clock upto 30MHz.

Am I missing anything here or is it something to do with FT8XX

Re: With 120MHz core clock (system clock) on MKV31F512VLL12, what is the maximum SPI clock i can generate and operate at? Please help on this question.

kerryzhou — Thu, 19 May 2016 02:10:50 GMT

Hi Sangamesh,

Did you check the FT8xx datasheet when it used as the slave, it can working with 30Mhz?

Actually, there has a easy way to check it, use the logic analyzer or the oscilloscope to check the SPI wave when working in the 30Mhz baud rate, whether the SPI communication wave is correct?

Have a great day,
Jingjing

Re: With 120MHz core clock (system clock) on MKV31F512VLL12, what is the maximum SPI clock i can generate and operate at? Please help on this question.

egoodii — Thu, 19 May 2016 03:23:21 GMT

There are, of course, many other elements to 'successful communication' than just clock rate -- every element has setup and hold to configured active edges, and probably 'inter command' minimums too. Check ALL parameters, both 'by design' AND on a scope VERY carefully to hit 'maximum possible rates'.

Re: With 120MHz core clock (system clock) on MKV31F512VLL12, what is the maximum SPI clock i can generate and operate at? Please help on this question.

kerryzhou — Thu, 19 May 2016 07:19:17 GMT

Hi Earl,

Did you check the communication data, when in 30Mhz baud rate, where it will stops? Master can't send or slave can't response or response the wrong data?

Have a great day,
Jingjing

Re: With 120MHz core clock (system clock) on MKV31F512VLL12, what is the maximum SPI clock i can generate and operate at? Please help on this question.

egoodii — Thu, 19 May 2016 10:45:19 GMT

Sorry, I am in no position to do a 'true check'. I don't even have an exact FTDI P/N, but just 'picking' FT812 and 3.3V-I/O timing I can only ASSUME the user has set the SPI port in the required 'Mode 0' and in 'Modified Timing Format' (MTFE=1) for 'late master sample', and with that there should be 'some margin':

Generated clock 'squareness' should be adequate, each half at 16.6+/-2ns into required 13ns.

MOSI: Kinetis output delay of 8.5ns FT812 input setup 3ns, only 11.5ns of >14.5ns half-period.

MISO: FT812 delay of 11ns, Kinetis input setup of 16.2ns -- much tighter at 27.2 of 33ns, less also some unspecified internal late-sample-point to SCK-fall delay in Kinetis in MTFE mode (figure 41-9) creating tSU_MS. Can someone at NXP give us a 'reasonable guess' for Table 35 DS7 (DSPI_SIN setup, but to SCK 'fall' in MTFE mode) so we can guesstimate setup margin? And in THIS path you also have to add the full round-trip delay Kinetis->FT812->Kinetis over what I might assume is a cable.

I don't see an FT812 spec for minimum inter-command delay -- doesn't mean there IS no such requirement.

And of course we can't vouch for the hardware-level interconnect details, including but not limited to series termination at the sources on ALL lines.

Re: With 120MHz core clock (system clock) on MKV31F512VLL12, what is the maximum SPI clock i can generate and operate at? Please help on this question.

sangameshvandal — Wed, 25 May 2016 20:55:45 GMT

Hi Earl,

Fogot to mention FTDI part used, it is FT810, could you please tell is it feasible to communicate at 30MHz

Re: With 120MHz core clock (system clock) on MKV31F512VLL12, what is the maximum SPI clock i can generate and operate at? Please help on this question.

egoodii — Thu, 26 May 2016 14:53:44 GMT

The FT810 is covered by the same datasheet, and so with the same timing info.

Have you just tried it in SPI mode 0 with MTFE set?

It would, of course, still be useful if someone at NXP gave us a 'reasonable guess' for Table 35 DS7 (DSPI_SIN setup, but to SCK 'fall' in MTFE mode).