FlexCan Receiving MB question

davidzhou — Mon, 14 Mar 2016 13:40:04 GMT

Hi,

Currently, I setup 8 receiving MBs from index 0 to 6. First 3 MBs is set to receive extended ID 0x0C20FF00 only, and next 3 MBs is setup to receive extended ID 0x0C21FF00 only. The last for any other extended ID.

The problem:

0x0C20FF00 is always received in MB[0]. - as expected

0x0C21FF00 and any other Ext IDs are received in MB[6]. - This is wrong. 0x0C21FF00 should be in MB[3].

If I set MB[6] to receive 0x0C22FF00 only, without any other changes,

0x0C20FF00 is always received in MB[0]. - as expected

0x0C21FF00 is received in MB[3]. - as expected.

0x0C22FF00 is received in MB[6]. - as expected.

Suppose MB[3-5] have higher priority than MB[6]. 0x0C21FF00 should be in the MB[3] instead of MB[6] in the first case. Why in MB[6] instead?

Here is the setup:

pCanReg->MCR |= (uint32_t)CAN_MCR_SRXDIS_MASK ; //Disable Self Reception

pCanReg->MCR |= (uint32_t)CAN_MCR_IRMQ_MASK ; //Enable Individual Mask and queue

pCanReg->MCR &= (~(uint32_t)CAN_MCR_IDAM_MASK); //Format A: One full ID (standard and extended)

pCanReg->MCR &= (~(uint32_t)CAN_MCR_RFEN_MASK); //Disable Rx FIFO

pCanReg->CTRL2 &= (~(uint32_t)CAN_CTRL2_RFFN_MASK) ;

//Initialize the Rx Individual Mask Registers

for (uint8_t mb=0; mb<NUM_OF_MB_USED_RX; mb++) {

FLEXCAN0_RXIMRn(mb) = g_dwMB_Masks[mb]; // 0: do not care 1: checked

}

pCanReg->MCR |= (uint32_t)CAN_MCR_SRXDIS_MASK ; //Disable Self Reception

pCanReg->MCR |= (uint32_t)CAN_MCR_IRMQ_MASK ; //Enable Individual Mask and queue

pCanReg->MCR &= (~(uint32_t)CAN_MCR_IDAM_MASK); //Format A: One full ID (standard and extended)

pCanReg->MCR &= (~(uint32_t)CAN_MCR_RFEN_MASK); //Disable Rx FIFO

pCanReg->CTRL2 &= (~(uint32_t)CAN_CTRL2_RFFN_MASK) ;

//Initialize the Rx Individual Mask Registers

for (uint8_t mb=0; mb<NUM_OF_MB_USED_RX; mb++) {

FLEXCAN0_RXIMRn(mb) = g_dwMB_Masks[mb]; // 0: do not care 1: checked

}

uint32_t g_dwMB_Masks[NUM_OF_MB_USED_RX] = {

0x1FFFFF00, 0x1FFFFF00, 0x1FFFFF00, //0-2: 0x0C20FF00 ( all SA )

0x1FFFFF00, 0x1FFFFF00, 0x1FFFFF00, //3-5: 0x0C21FF00 ( all SA )

0x1FFFFF00, //6:

//6: if only for 0x0C22FF00, 3-5 Rx-ed ok

//6: if for any other Ext IDs, 0x0C21FF00 goes to MB[6]

Thank you,

David Zhou

Re: FlexCan Receiving MB question

davidzhou — Mon, 14 Mar 2016 14:23:45 GMT

Continued:

the CANx_CTRL2[RFFN] is ambiguous to me. Rx FIFO is disabled, and CANx_CTRL2[RFFN] is set to 0. But why the Number of Rx FIFO filters

is still 8, instead of 0, in the table [CANx_CTRL2 field descriptions] on Page 1656?

Thank you,

David

Re: FlexCan Receiving MB question

davidzhou — Mon, 14 Mar 2016 14:58:23 GMT

I found the problem. It is in my processing code, which only MB[0] is read and processed. Other messages are not read and processed, which causes the corresponding MB full, and it goes to MB[6].

Thank you,

David

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FlexCan Receiving MB question

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