FBLIP Clock Mode of KEA-128?

vigneshbalaji — Mon, 30 May 2016 20:13:41 GMT

Hi,

I want to know what is the maximum bus Clock that can be run in FLL bypassed internal low power(FBLIP) Mode???

Re: FBLIP Clock Mode of KEA-128?

Robin_Shen — Wed, 01 Jun 2016 06:05:57 GMT

Hi VIGNESH,

In FLL bypassed internal low-power mode, the ICSOUT clock is derived from the internal reference clock and the FLL is disabled. The internal reference clock is enabled.

You can refer the "Figure 5-1. Clocking diagram" in KEA128RM.pdf.

If all these Dividers(BDIV DIV1 DIV2) divides by 1, the frequency of Bus Clock will same as IRC.

Then you can find the ICS specifications in S9KEA128P80M48SF0.pdf.

Best Regards,

Robin

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FBLIP Clock Mode of KEA-128?

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