Kinetis Microcontrollers中的主题 Re: K20: FTM clock divided by 2

K20: FTM clock divided by 2

michaelheidinge — Wed, 11 May 2016 11:16:41 GMT

Hi,

I use the K22 MCU, configured the clock to 80MHz.

For configuring the clock I used USBDM default setup code.

Now, I want to check if the clock is configured right:

void FTM_EPWM(void){
    // Enable clock to TIMER FTM0
   SIM->SCGC6 |= SIM_SCGC6_FTM0_MASK;
   // Enable clock to port pins used by FTM0, we use port C
   SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
   // Select FTM0_CH0 and FTM0_CH1 pins
 //  SIM->SOPT8 |= (SIM_SOPT8_FTM0OCH0SRC_MASK|SIM_SOPT8_FTM0OCH1SRC_MASK);
   //Set pin to right output
   PORTC->PCR[1] = PORT_PCR_MUX(4)| PORT_PCR_DSE_MASK; //FTM0_CH0
   PORTC->PCR[2] = PORT_PCR_MUX(4)| PORT_PCR_DSE_MASK; //FTM0_CH1
   FTM0->MODE&=~(FTM_MODE_WPDIS_MASK);
   FTM0->MODE|=(FTM_MODE_FTMEN_MASK);
    /* Configure timers for edge aligned PWM High True Pulses */
//printf("FTM2_ Edge_Aligned Test 1\r\n");
    //printf("Please check the waveform, 90% Hign Ture EPWM\r\n");
    FTM0->MOD = 79;
    FTM0->CONTROLS[0].CnSC= (FTM_CnSC_MS(0b10) | FTM_CnSC_ELS(0b10));   /* No Interrupts; High True pulses on Edge Aligned PWM */
    FTM0->CONTROLS[1].CnSC= 0x28;
    FTM0->CONTROLS[0].CnV=40;  /* 90% pulse width */
    FTM0->CONTROLS[1].CnV=40;
    FTM0->SC=FTM_SC_CLKS(0b01)|FTM_SC_PS(0);     /* Edge Aligned PWM running from BUSCLK / 1 */
                                                                                          // 50% Duty Cycle
    FTM0->SC = FTM_SC_CLKS(1);
}

Now, I see a 500kHz Clock instead of a 1MHz clock. Any idea where the divide by 2 hides?

-Michael

Re: K20: FTM clock divided by 2

jeremyzhou — Thu, 12 May 2016 09:20:50 GMT

Hi Michael,

After had a brief look through the code above, I hasn't found any thing wrong with it until now.

So I'd highly recommend that you can output the system clock through the CLKOUT pin, then illustrate the output wave by using oscilloscope.

By through the way, you can confirm the MCU whether run at the 80 MHz or not.

I'm looking forward to your reply.
Have a great day,

Ping

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Re: K20: FTM clock divided by 2

michaelheidinge — Fri, 13 May 2016 08:11:57 GMT

Dear Jeremy,

first thanks for your support.

I use the Freedom Board K22 (512Kb) here.

I verfied the internal clock to 80Mhz using the following function.

void clkout_init(void){
    //Configure PCR[3] to clkout.
     PORTC->PCR[3] = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; //FTM0_CH0
     SIM->SOPT2&=~SIM_SOPT2_CLKOUTSEL_MASK;
     SIM->SOPT2|=SIM_SOPT2_CLKOUTSEL(0);
}

On the oscilosocpe I could see the 80Mhz.

Now I checked again the clock output using the following code:

void FTM_EPWM(void){
    // Enable clock to TIMER FTM0
   SIM->SCGC6 |= SIM_SCGC6_FTM0_MASK;
   // Enable clock to port pins used by FTM0, we use port C
   SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
   //Set pin to right output
   PORTC->PCR[1] = PORT_PCR_MUX(4)| PORT_PCR_DSE_MASK; //FTM0_CH0
   PORTC->PCR[2] = PORT_PCR_MUX(4)| PORT_PCR_DSE_MASK; //FTM0_CH1
   FTM0->MODE&=~(FTM_MODE_WPDIS_MASK);
   FTM0->MODE|=(FTM_MODE_FTMEN_MASK);
    FTM0->MOD = 79;
    FTM0->CONTROLS[0].CnSC= (FTM_CnSC_MS(0b10) | FTM_CnSC_ELS(0b10));   /* No Interrupts; High True pulses on Edge Aligned PWM */
    FTM0->CONTROLS[1].CnSC= (FTM_CnSC_MS(0b01) | FTM_CnSC_ELS(0b01));
    FTM0->CONTROLS[0].CnV=40;  /* 50% pulse width */
    FTM0->CONTROLS[1].CnV=40;
    FTM0->SC=FTM_SC_CLKS(0b01)|FTM_SC_PS(0);     /* Edge Aligned PWM running from System Clock / 1 */
}

But, still CH1 500kHz and CH2 250 kHz.

Double the frequency is expected.

Is the SYSTEMCLOCK really the souce, or could it be, that the source is busclock?

Could you please help?

-Michael

Re: K20: FTM clock divided by 2

michaelheidinge — Fri, 13 May 2016 12:34:10 GMT

Ok, here comes the solution.

Flextimer FTM is not clocked by the System Clk (OUTDIV1), instead it's actually clocked from the Busclock (OUTDIV2).

The Reference sheet clearly tells, it would be the System Clock, that is not true.

Questions to NXP:

1. I checked the errata. Nothing found. Where can I report this issue?

2. Is it okay, to run the Busclock at 120MHz, to compensate that flaw?

Here comes the SIM->SDID for reproducing the error:

Hex:0x22001e95

Binary:100010000000000001111010010101

Re: K20: FTM clock divided by 2

egoodii — Fri, 13 May 2016 14:19:34 GMT

The problem is the WAY in which the reference manuals for these parts are 'assembled'. That is, the specific 'peripheral' sections are written 'very generically', with NO chip-specifics included. So, for instance, the FTM section's 'view' of 'clock' would be with a 'system clock' for IT as a system, not the whole CHIP system. Unfortunately, for all 'chip details' you have to constantly refer back to section '3' that details how each subsystem has been 'glued together' to make the whole. In this particular case, section 3.8.2.2 gives you exactly that info:

By default each FTM is clocked by the internal bus clock (the FTM refers to it as system clock).

This kind of confusion gets worse, for instance, in the description of the SPI module. Clocking examples SPECIFICALLY mention '100MHz' everywhere, which might lead you to the OBVIOUS conclusion you could use the 100MHz 'system' clock as a source, but once again the ACTUAL clock is BUSCLK, and thus LIMITED to 50MHz on <=100MHz CPUs (or 60MHz on 120/180MHz CPUs, with 75MHz on 150MHz CPUs being the FASTEST allowed)....makes for 'not very helpful' examples.

Re: K20: FTM clock divided by 2

jeremyzhou — Mon, 16 May 2016 01:58:03 GMT

Hi Michael,

Thanks for your reply and I'm glad to hear that you already found out the root cause of the issue. About the other questions, please check them below.

1. I checked the errata. Nothing found. Where can I report this issue?

I'll report this doc bug to the Doc team for checking later.

2. Is it okay, to run the Busclock at 120MHz, to compensate that flaw?

I'd like to know what exactly product you choose and can you share the product number with me?
Have a great day,
Ping

Re: K20: FTM clock divided by 2

egoodii — Mon, 16 May 2016 12:48:43 GMT

I don't know that you could call this an 'errata'. This is clearly the 'documentation process' Freescale chose to follow, although I agree that it is 'fundamentally flawed' as a concept.

As I indicated, if you move to a platform with one of the 150MHz 'K' CPUs you can get a 75MHz BusClock, but THAT is as FAST as would be available AFAIK. These limits are straight from the datasheet as fBUS. As with most specs, you can possibly 'push' that a little in a controlled environment, but I would NEVER expect you could get to 120MHz on ANY Kinetis chip.

May I ask what drives your need for 'extreme FTM speed'?

Re: K20: FTM clock divided by 2

michaelheidinge — Tue, 17 May 2016 07:10:14 GMT

so far, so clear, the manual is indeed confusing here, but now I know (for least) the root cause.

The product used in the MK22FN512 from the Freedom eval kit.

Checking the KV3x Energy Control series, I see the same problem, that the CLK speed will be limited to 60MHz.

The FTM speed is required to get a decent resoluion for LLC-Converter control.

I want that the converter gets a decent resolutio. Switching frequency ranges from 100kHz to 1MHz.

And 60 count vs 120 counts is a difference.

Thanks for the support Jeremy and Earl.