<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic SPI FIFO INITIALIZATION in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-FIFO-INITIALIZATION/m-p/454046#M27043</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Can anyone please give me SPI FIFO initialization .The one I have made is not working properly.I am also posting my spi fifo initialization&lt;/P&gt;&lt;P&gt;void spi_master_fifo_init()&lt;/P&gt;&lt;P&gt;{&lt;/P&gt;&lt;P&gt;&amp;nbsp; SIM_SCGC6 |= SIM_SCGC6_DSPI0_MASK;&lt;/P&gt;&lt;P&gt;&amp;nbsp; // first set the spi2_mcr &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; spi_pin_mapping();&lt;/P&gt;&lt;P&gt;&amp;nbsp; // MASTER MODE ,Continuous clock generation, peri chip select signal, when rx data overflow overwrite the shift register, all the chip select uses high signal for deactivating, doze mode is disabled, enalbe DSPI clocks always and is not controlled by external digital pins, tx and rx are enabled&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp; SPI0_MCR = ((HALT) | (MODULE_DISABLE));&lt;/P&gt;&lt;P&gt;&amp;nbsp; SPI0_MCR = ((TX_DISABLE)|(MASTER_MODE)|(RX_DISABLE)|(SPI_MCR_ROOE_MASK)|(SPI_MCR_CLR_TXF_MASK)|SPI_MCR_CLR_RXF_MASK|(SPI_MCR_DCONF(0x00))|(SPI_MCR_CONT_SCKE_MASK &amp;amp; 0x01)|(SPI_MCR_PCSIS(31)));&lt;/P&gt;&lt;P&gt;&amp;nbsp; SPI0_CTAR0 = (SPI_CTAR_DBR_MASK &amp;amp; 0x00) | (SPI_CTAR_FMSZ(0x07)) | (SPI_CTAR_PDT(0x00)) | (SPI_CTAR_BR(0x08)) | (INACTIVE_CLOCK_POLARITY_LOW) | (CLOCK_PHASE_CAPTURE_ON_LOW) | (SPI_CTAR_PBR(0x03)) | (SPI_CTAR_PCSSCK(0x02) | (SPI_CTAR_PASC(0x00)) | (SPI_CTAR_CSSCK(0x06)) | (SPI_CTAR_ASC(0)) | (SPI_CTAR_PDT(0x00)) | (SPI_CTAR_DT(0))) ; // mode 0 operation&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;BUT its not working properly.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 04 Jul 2015 08:33:26 GMT</pubDate>
    <dc:creator>deepanshgoyal</dc:creator>
    <dc:date>2015-07-04T08:33:26Z</dc:date>
    <item>
      <title>SPI FIFO INITIALIZATION</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-FIFO-INITIALIZATION/m-p/454046#M27043</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Can anyone please give me SPI FIFO initialization .The one I have made is not working properly.I am also posting my spi fifo initialization&lt;/P&gt;&lt;P&gt;void spi_master_fifo_init()&lt;/P&gt;&lt;P&gt;{&lt;/P&gt;&lt;P&gt;&amp;nbsp; SIM_SCGC6 |= SIM_SCGC6_DSPI0_MASK;&lt;/P&gt;&lt;P&gt;&amp;nbsp; // first set the spi2_mcr &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; spi_pin_mapping();&lt;/P&gt;&lt;P&gt;&amp;nbsp; // MASTER MODE ,Continuous clock generation, peri chip select signal, when rx data overflow overwrite the shift register, all the chip select uses high signal for deactivating, doze mode is disabled, enalbe DSPI clocks always and is not controlled by external digital pins, tx and rx are enabled&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp; SPI0_MCR = ((HALT) | (MODULE_DISABLE));&lt;/P&gt;&lt;P&gt;&amp;nbsp; SPI0_MCR = ((TX_DISABLE)|(MASTER_MODE)|(RX_DISABLE)|(SPI_MCR_ROOE_MASK)|(SPI_MCR_CLR_TXF_MASK)|SPI_MCR_CLR_RXF_MASK|(SPI_MCR_DCONF(0x00))|(SPI_MCR_CONT_SCKE_MASK &amp;amp; 0x01)|(SPI_MCR_PCSIS(31)));&lt;/P&gt;&lt;P&gt;&amp;nbsp; SPI0_CTAR0 = (SPI_CTAR_DBR_MASK &amp;amp; 0x00) | (SPI_CTAR_FMSZ(0x07)) | (SPI_CTAR_PDT(0x00)) | (SPI_CTAR_BR(0x08)) | (INACTIVE_CLOCK_POLARITY_LOW) | (CLOCK_PHASE_CAPTURE_ON_LOW) | (SPI_CTAR_PBR(0x03)) | (SPI_CTAR_PCSSCK(0x02) | (SPI_CTAR_PASC(0x00)) | (SPI_CTAR_CSSCK(0x06)) | (SPI_CTAR_ASC(0)) | (SPI_CTAR_PDT(0x00)) | (SPI_CTAR_DT(0))) ; // mode 0 operation&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;BUT its not working properly.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 04 Jul 2015 08:33:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-FIFO-INITIALIZATION/m-p/454046#M27043</guid>
      <dc:creator>deepanshgoyal</dc:creator>
      <dc:date>2015-07-04T08:33:26Z</dc:date>
    </item>
    <item>
      <title>Re: SPI FIFO INITIALIZATION</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-FIFO-INITIALIZATION/m-p/454047#M27044</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Deepansh,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Which MCU are you using?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Earl.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 10 Jul 2015 20:55:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-FIFO-INITIALIZATION/m-p/454047#M27044</guid>
      <dc:creator>EarlOrlando</dc:creator>
      <dc:date>2015-07-10T20:55:28Z</dc:date>
    </item>
  </channel>
</rss>

