<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: How to flash a kinetis using SWD protocol in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/How-to-flash-a-kinetis-using-SWD-protocol/m-p/454012#M27042</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;One more obstacle found..&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Flash module (FTFA) registers FTFA_FCCOB[0..B] need to be written during flashing. I struggled a while with a problem that the registers did not read back the written value, but always returned zero.&lt;/P&gt;&lt;P&gt;The solution is to disable COP watchdog in SIM module, right after the reset is released. Then the flashing procedures work as documented.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This information is missing from AN4835. Suggest to update that too.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR, -Topi&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 09 Nov 2015 09:00:12 GMT</pubDate>
    <dc:creator>topir</dc:creator>
    <dc:date>2015-11-09T09:00:12Z</dc:date>
    <item>
      <title>How to flash a kinetis using SWD protocol</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/How-to-flash-a-kinetis-using-SWD-protocol/m-p/454008#M27038</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am trying to program the flash of MKL05 using SWD (with GPIO).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. The KL05 Sub-Family Reference Manual, Rev 3.1, November 2012 states at page 139, that AHB-AP is connected to SW-DP. But, from the ARM infocenter I could not find AHB-AP documentation related to Cortex-M0 (Only M1, M3 and M4). Which version of AHB-AP documentation should I refer to?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2. I have succesfully accessed MDM-AP, can read IDR (0x04770031) &amp;amp; Status, and can write/read Control registers. I can also read IDR of AHB-AP. But after writing 0x00000000 to AHB-AP.TAR, the SW-DP.CTRL/STAT shows STICKYERR set (first read of CTRL/STAT after TAR write is 0x00000040, second read of CTRL/STAT after TAR write is 0x00000060). Any AP access after this returns ACK = 4 (fail).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2.5. The AHB-AP.CSW == 0x03000042. Based on Cortex-M1 documentation, bits 27:24 are HPROT[3:0].&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Any ideas what is causing this and how to proceed to access Flash Memory Module (FTFA)?&amp;nbsp; Could it be a missing (power) enable somewhere?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR, -Topi&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 03 Nov 2015 14:41:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/How-to-flash-a-kinetis-using-SWD-protocol/m-p/454008#M27038</guid>
      <dc:creator>topir</dc:creator>
      <dc:date>2015-11-03T14:41:11Z</dc:date>
    </item>
    <item>
      <title>Re: How to flash a kinetis using SWD protocol</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/How-to-flash-a-kinetis-using-SWD-protocol/m-p/454009#M27039</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;2. Sorry, the AHB-AP IDR is 0x04770031. MDM-AP IDR is 0x001C0020.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR, -Topi&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 03 Nov 2015 15:18:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/How-to-flash-a-kinetis-using-SWD-protocol/m-p/454009#M27039</guid>
      <dc:creator>topir</dc:creator>
      <dc:date>2015-11-03T15:18:58Z</dc:date>
    </item>
    <item>
      <title>Re: How to flash a kinetis using SWD protocol</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/How-to-flash-a-kinetis-using-SWD-protocol/m-p/454010#M27040</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Found the problem:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The picture on page 139 of KL05 Sub-Family Reference Manual, Rev. 3.1, November 2012&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.freescale.com/files/32bit/doc/ref_manual/KL05P48M48SF1RM.pdf?fpsp=1&amp;amp;WT_TYPE=Reference%20Manuals&amp;amp;WT_VENDOR=FREESCALE&amp;amp;WT_FILE_FORMAT=pdf&amp;amp;WT_ASSET=Documentation&amp;amp;fileExt=.pdf" title="http://cache.freescale.com/files/32bit/doc/ref_manual/KL05P48M48SF1RM.pdf?fpsp=1&amp;amp;WT_TYPE=Reference%20Manuals&amp;amp;WT_VENDOR=FREESCALE&amp;amp;WT_FILE_FORMAT=pdf&amp;amp;WT_ASSET=Documentation&amp;amp;fileExt=.pdf"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/KL05P48M48SF1RM.pdf?fpsp=1&amp;amp;WT_TYPE=Reference%20Manuals&amp;amp;WT_VENDOR=F…&lt;/A&gt;&lt;/P&gt;&lt;P&gt;States that the address range of MDM-AP is 0x00 .. 0x3F.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;ARM documentation (MEM-AP) states the address range being 0x00 .. 0xFC (2 LSBs being zero).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I tried to access AHB-AP with address 0x04 (TAR register), but actually it wrote to address 0x10 (BD0), which caused bus error, I guess.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;FREESCALE: You should correct the Keystone documentation to express the MDM-AP addresses in the same address format as ARM is doing. Agree?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR, -Topi&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 04 Nov 2015 09:08:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/How-to-flash-a-kinetis-using-SWD-protocol/m-p/454010#M27040</guid>
      <dc:creator>topir</dc:creator>
      <dc:date>2015-11-04T09:08:02Z</dc:date>
    </item>
    <item>
      <title>Re: How to flash a kinetis using SWD protocol</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/How-to-flash-a-kinetis-using-SWD-protocol/m-p/454011#M27041</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Topi Rinkinen:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Glad to see you found the issue. The addresses in the Reference Manual [0x00/0x01/0x3F] actually refer to the bits SELECT[7:2] as implied by the comments:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_0.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/4603i93FAAEA1BDDF6AB9/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_0.png" alt="pastedImage_0.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So with the 2-bits shift the actual addresses are as you found [0x00/0x04/0xFC]. I agree this can be confusing.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Let me pass your feedback, although the whole range of Kinetis manuals use the same scheme, so this would need a massive update effort.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards!&lt;/P&gt;&lt;P&gt;Jorge Gonzalez&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 06 Nov 2015 18:04:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/How-to-flash-a-kinetis-using-SWD-protocol/m-p/454011#M27041</guid>
      <dc:creator>Jorge_Gonzalez</dc:creator>
      <dc:date>2015-11-06T18:04:51Z</dc:date>
    </item>
    <item>
      <title>Re: How to flash a kinetis using SWD protocol</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/How-to-flash-a-kinetis-using-SWD-protocol/m-p/454012#M27042</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;One more obstacle found..&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Flash module (FTFA) registers FTFA_FCCOB[0..B] need to be written during flashing. I struggled a while with a problem that the registers did not read back the written value, but always returned zero.&lt;/P&gt;&lt;P&gt;The solution is to disable COP watchdog in SIM module, right after the reset is released. Then the flashing procedures work as documented.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This information is missing from AN4835. Suggest to update that too.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR, -Topi&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 09 Nov 2015 09:00:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/How-to-flash-a-kinetis-using-SWD-protocol/m-p/454012#M27042</guid>
      <dc:creator>topir</dc:creator>
      <dc:date>2015-11-09T09:00:12Z</dc:date>
    </item>
  </channel>
</rss>

