Kinetis MicrocontrollersのトピックRe: K64F120M communication with Micrel KSZ8863 problem

K64F120M communication with Micrel KSZ8863 problem

wulinweng — Fri, 24 Jul 2015 07:45:43 GMT

Now our project encountered a problem: the k64 cpu want to
communicate with micrel ksz8863 through SMI mode to visit the internal register
from 0~198. According to the SMI mode visit protocol, the different is below:

PAGE 1172 in attached k64 cpu
datasheet:

OP= 00 WRITE/OP=11 READ

And in 8863 datasheet (page33 ):

OP = 00 read/write function

It seems the two datasheet about
the OP is contradictory.

Do you have any guidance or
information according to your experience?

Re: K64F120M communication with Micrel KSZ8863 problem

mjbcswitzerland — Fri, 24 Jul 2015 18:37:35 GMT

If you require a professional solution to your problem you can obtain all that you require from the uTasker project for the K64.

It contains Micrel SMI mode of operation (this cannot be performed with the usual MDIO mode) and also supports the KSZ8863 tail-tagging mode to allow it to be used as if there were two independent Ethernet controllers.

The uTasker TCP/IP stack support multi-homed network operation, which can be achieved with the K64 and this PHY.

Regards

Mark

Kinetis: µTasker Kinetis support

K64: µTasker Kinetis FRDM-K64F support / µTasker Kinetis TWR-K64F120M support / µTasker Kinetis TWR-K65F180M support

For the complete "out-of-the-box" Kinetis experience and faster time to market

Re: K64F120M communication with Micrel KSZ8863 problem

wulinweng — Tue, 28 Jul 2015 01:53:42 GMT

Dear Mark,

Thank you so much for your quick reply.

I have download the uTasker source code and checked the source code about the SMI mode, but the result is that the SMI mode in the source code used OP = 01/10,

So I think it is the MIIM mode not SMI mode indeed.

Now we want to use OP=00 to read/write internal register 0-198 from ksz8863.

BR,

Re: K64F120M communication with Micrel KSZ8863 problem

mjbcswitzerland — Tue, 28 Jul 2015 02:29:19 GMT

In the code you need to search for the define PHY_MICREL_SMI.

For writes the code used is (MII_TA | MII_ST), instead of (MII_TA | MII_ST | WRITE_OP), as used for normal MIIM: fnMIIwrite().

For reads it is not possible to use the MIIM so you will find that the reads are performed by bit-banging the interface: fnMIIread().

In the solution the MIIM mode is used when the routines are passed an address != 0. When the address is 0, the SMI mode is used instead. Therefore you can certainly find this if you search.

Regards

Mark

Kinetis: µTasker Kinetis support

K64: µTasker Kinetis FRDM-K64F support / µTasker Kinetis TWR-K64F120M support / µTasker Kinetis TWR-K65F180M support

For the complete "out-of-the-box" Kinetis experience and faster time to market