<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Kinetis K10 Clocking Question in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Kinetis-K10-Clocking-Question/m-p/195145#M2567</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi NB,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;That´s right, you can´t clock the core at 72MHz and the bus at 50MHz. In the same table (Table 5.1)&amp;nbsp; says that the bus clock´s max frequency is up to 50MHz, then writing 0x00 to OUTDIV2 will exceed the limit for Bus Clock.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope this Helps.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 30 Nov 2012 19:46:43 GMT</pubDate>
    <dc:creator>adriansc</dc:creator>
    <dc:date>2012-11-30T19:46:43Z</dc:date>
    <item>
      <title>Kinetis K10 Clocking Question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Kinetis-K10-Clocking-Question/m-p/195144#M2566</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm reading a K10 ref manual (Doc #K10P64M72SF1RM, Rev.1) and I wanted to get clarification on the bus clocking.&amp;nbsp; Table 5.1 in section 5.4.1 shows that the MCGOUTCLK can be run up to 72 MHz.&amp;nbsp; It also states that the bus clock can run up to a max of 50MHz (based on OUTDIV2 per the previous section).&amp;nbsp; In order to do this however, it looks like you'd have to run the MCGOUTCLK at 50MHz and let OUTDIV2 correspond to a divider of 1.&amp;nbsp; Am I understanding this correctly?&amp;nbsp; So... can't clock the core at 72MHz and the bus at 50MHz in the same application, correct?&amp;nbsp;&amp;nbsp; What happens when I have OUTDIV1 set such that the core is running at 72MHz, and I let OUTDIV2 = 0x0 (divider of 1) for the bus clock?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;NB&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 Nov 2012 15:06:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Kinetis-K10-Clocking-Question/m-p/195144#M2566</guid>
      <dc:creator>nba916</dc:creator>
      <dc:date>2012-11-30T15:06:06Z</dc:date>
    </item>
    <item>
      <title>Re: Kinetis K10 Clocking Question</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/Kinetis-K10-Clocking-Question/m-p/195145#M2567</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi NB,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;That´s right, you can´t clock the core at 72MHz and the bus at 50MHz. In the same table (Table 5.1)&amp;nbsp; says that the bus clock´s max frequency is up to 50MHz, then writing 0x00 to OUTDIV2 will exceed the limit for Bus Clock.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope this Helps.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 Nov 2012 19:46:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/Kinetis-K10-Clocking-Question/m-p/195145#M2567</guid>
      <dc:creator>adriansc</dc:creator>
      <dc:date>2012-11-30T19:46:43Z</dc:date>
    </item>
  </channel>
</rss>

