topic Maximum ADC sampling rate when triggered by PDB in Kinetis Microcontrollers

Maximum ADC sampling rate when triggered by PDB

sergeisharonov — Fri, 04 Sep 2015 20:18:28 GMT

Hello,

Kinetis ADC takes longer to acquire the first sample in a sequence due to SFCAdder effect. Apparently when triggering ADC by PDB this first sample limits maximum sampling rate. If PDB interval is shorter than this first extended ADC sample (but longer then subsequent "normal" samples), PDB will stop and not trigger until the error is cleared from PDB_CHnS register.

In my case this changes required number of cycles per sample from 27 to ~32, e.g. 19% drop in maximum sampling rate. Is there a way to avoid this? Note that I cannot free-run ADC as I use PDB to synchronize ADC and DAC.

Regards,

Sergei

Re: Maximum ADC sampling rate when triggered by PDB

jeremyzhou — Wed, 09 Sep 2015 06:46:23 GMT

Hi Sergei,

I'd highly recommend you to select the back-to-back operation to get the maximum ADC sampling rate.

And please learn more information about the back-to-back operation in the reference manual.
Have a great day,
Ping

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