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    <title>Kinetis MicrocontrollersのトピックRe: TWR manual vs. k60 Reference manual</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/TWR-manual-vs-k60-Reference-manual/m-p/151923#M228</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;1) It uses SPI2 on the K60. But it's connected to the pins defined as "SPI0" as seen by the elevator. The K60 SPI0 pins are being used for something else (with all the muxing Kinetis uses) on the board, so the K60 SPI2 module was designated instead to go out to the elevator SPI pins.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;This means any other tower module you have that is connected to SPI0 on the elevator ( B44 - B48) will be connected to the K60 SPI2 module. I understand how that's confusing, but I hope that cleared it up.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;2) It should be SPI0 without the D. It's due to a register name typo on the SPI0 clock gating bit, as originally it was going to be called DSPI, and then later the name was changed to just SPI. It will be fixed in the next rev of the manual (which is what the header files are generated against) and then the header files will be updated accordingly.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;-amh&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 22 Jul 2011 03:31:39 GMT</pubDate>
    <dc:creator>anthony_huereca</dc:creator>
    <dc:date>2011-07-22T03:31:39Z</dc:date>
    <item>
      <title>TWR manual vs. k60 Reference manual</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/TWR-manual-vs-k60-Reference-manual/m-p/151919#M224</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am confused&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;in TWR-K60N512&amp;nbsp; Users manual on page 16, there are side B pins B44 - B48 description as SPI_0 and usage as PTD14,13,11,15,12&lt;/P&gt;&lt;P&gt;but in K60 reference manual on page 239 are those pins on port D used for SPI_2.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Second case is about MK60N512VMD100﻿.h&lt;/P&gt;&lt;P&gt;Why is the mask for&amp;nbsp;SPI_0﻿ in&amp;nbsp; /* SCGC6 Bit Fields */﻿&lt;/P&gt;&lt;P&gt;defined as&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;SIM_SCGC6_DSPI0_MASK&lt;/STRONG&gt;﻿&lt;/P&gt;&lt;P&gt;and masks for other SPIs are normal&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;SIM_SCGC6_SPI1_MASK﻿&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;SIM_SCGC3_SPI2_MASK&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;what the &lt;STRONG&gt;D&lt;/STRONG&gt; before SPI0 means&amp;nbsp;?﻿&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Lukas&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 20 Jul 2011 18:40:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/TWR-manual-vs-k60-Reference-manual/m-p/151919#M224</guid>
      <dc:creator>lukas</dc:creator>
      <dc:date>2011-07-20T18:40:45Z</dc:date>
    </item>
    <item>
      <title>Re: TWR manual vs. k60 Reference manual</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/TWR-manual-vs-k60-Reference-manual/m-p/151920#M225</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I find the DSPI description in reference manual on page 1395﻿ it was stupid question&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 20 Jul 2011 19:08:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/TWR-manual-vs-k60-Reference-manual/m-p/151920#M225</guid>
      <dc:creator>lukas</dc:creator>
      <dc:date>2011-07-20T19:08:41Z</dc:date>
    </item>
    <item>
      <title>Re: TWR manual vs. k60 Reference manual</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/TWR-manual-vs-k60-Reference-manual/m-p/151921#M226</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;PRE&gt;#define SIM_SCGC6_DSPI0_MASK                     0x1000u#define SIM_SCGC6_DSPI0_SHIFT                    12#define SIM_SCGC6_SPI1_MASK                      0x2000u#define SIM_SCGC6_SPI1_SHIFT                     13

#define SIM_SCGC3_SPI2_MASK                      0x1000u
#define SIM_SCGC3_SPI2_SHIFT                     12&lt;/PRE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;not that stupid....&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;what is the difference between DSPI0 and SPI1 ? Refering to manual, every SPI module (3 in this device) is a DSPI...&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;STRONG&gt;49.1.3 DSPI Configurations&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;The DSPI module always operates in SPI configuration.&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;BR /&gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;why is then only SPI0 defined as DSPI ?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Oct 2020 08:55:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/TWR-manual-vs-k60-Reference-manual/m-p/151921#M226</guid>
      <dc:creator>pende</dc:creator>
      <dc:date>2020-10-29T08:55:22Z</dc:date>
    </item>
    <item>
      <title>Re: TWR manual vs. k60 Reference manual</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/TWR-manual-vs-k60-Reference-manual/m-p/151922#M227</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;and the&lt;/P&gt;&lt;P&gt;base pointer and registers of SPI0 &amp;nbsp;are without D &amp;nbsp;&lt;IMG alt=":smileyvery-happy:" class="emoticon emoticon-smileyvery-happy" id="smileyvery-happy" src="http://freescale.i.lithium.com/i/smilies/16x16_smiley-very-happy.gif" title="Smiley Very Happy" /&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;SPI0_BASE_PTR﻿&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 21 Jul 2011 12:44:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/TWR-manual-vs-k60-Reference-manual/m-p/151922#M227</guid>
      <dc:creator>lukas</dc:creator>
      <dc:date>2011-07-21T12:44:46Z</dc:date>
    </item>
    <item>
      <title>Re: TWR manual vs. k60 Reference manual</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/TWR-manual-vs-k60-Reference-manual/m-p/151923#M228</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;1) It uses SPI2 on the K60. But it's connected to the pins defined as "SPI0" as seen by the elevator. The K60 SPI0 pins are being used for something else (with all the muxing Kinetis uses) on the board, so the K60 SPI2 module was designated instead to go out to the elevator SPI pins.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;This means any other tower module you have that is connected to SPI0 on the elevator ( B44 - B48) will be connected to the K60 SPI2 module. I understand how that's confusing, but I hope that cleared it up.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;2) It should be SPI0 without the D. It's due to a register name typo on the SPI0 clock gating bit, as originally it was going to be called DSPI, and then later the name was changed to just SPI. It will be fixed in the next rev of the manual (which is what the header files are generated against) and then the header files will be updated accordingly.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;-amh&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 22 Jul 2011 03:31:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/TWR-manual-vs-k60-Reference-manual/m-p/151923#M228</guid>
      <dc:creator>anthony_huereca</dc:creator>
      <dc:date>2011-07-22T03:31:39Z</dc:date>
    </item>
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