DediProg SF600 Plus EzPort FRDM-K64 - Not working - Help

techscale — Thu, 15 Oct 2015 00:28:33 GMT

EzPort K64 Hardware Configuration

Introduction

This document describes installing and testing of SF600 Plus DediProgrammer with Freescale K64 processor on FRDM K64 evaluation board.

The purpose of this document is to determine if the SF600 Plus is compatible with EzPort feature of the MK64FN1M0VLL12 processor as claimed by the manufacturer.

I've purchased a SF600 Plus programmer and below are my notes on setting up the hardware and software. I’m following the directions provided by DediProg on setting up EzPort in the EzPortsupport.pdf document. Unfortunately, the directions are a bit vague and I’ve been unable to get the programmer to work.

I first tried to get the programmer working on my customer board that I've been programming / debugging with a Segger J-Link.

I wanted to use EzPort to program boards in production which is why I selected teh DediProg SF600 Plus as it operates in a stand alone mode.

EM100-Split-Cable - PN EM-SP-CB

http://siliconkit.com/ocart/index.php?route=product/product&path=20_26&product_id=67

SF600 PLUS SPI FLASH IC PROGRAMMER

http://siliconkit.com/ocart/index.php?route=product/product&path=20&product_id=288

FRDM-K64F Freedom Development Platform

EzPort_Support.pdf

This document contains set up info to Program and I hope Read Freescale MCU

Installing Dediport Driver

Follow directions provided in DediProg SF software user manual. Installation requires manually installing driver. Must tell operating system where inf file on CD or drive.

Installing SF600 desktop software

Run SF6.0.4.39_Beta.msi software and follow prompts. Seems to be working.

This is the Engineering software – there is also a production software

So the desktop software seems to be working –

Hardware Connection Table

Connecting SF600 to K64 chip via SWD connector on my board. Below are connection details

Table 2 from DediProg EzPort user manual for SF600

K64 pins vs SWD header on board vs SF600 DediProgammer pinout

K64 Pin Name	K64 Pin #	K64 EZP Pin Name	K64 SWD Pin Name	K64 JTAG Pin Name	sWD Header PIN on Board	SF600 Pin Name	SF600 Pin #	SF600 Split Cable Color	Comment
PTA3 -	37		SWD_DIO	JTAG TMS	2
PTA0	34	EZP_CLK EZP_CK?	SWD CLK	JTAG TCLK	4	CLK	8	Gray
PTA2	36	EZP_D0 EZP_Q?	SWO /EXTa /TRACECTL	JTAG TDO	6	MISO	5	green
PTA4 or NMI	38	EZP_CS	N/A			CS 1	3	orange	Connected with SW3 on FRDM-K64
PTA1	35	EZP_DI EZP_D?	NC/EXTb	JTAG TDI		MOSI	10	black	unconnected to SWD connector but on pin 8 of J1 (2x8)on FRDM-K64
					3 and 5 GND	GND	9	white
Reset	52			nRESET	10	CS 2	2	red

Connecting Dediport to Target FRDM-K64

Most of the connection points required for EzPort on the FRDM-K64 board are exposed on the Serial Wire Debug (SWD) connector and on the Ardinuo headers.

The SWD connector is used a segger j-link to load and debug software.

Before connecting the programmer to the FRDM-K64, scratch out the trace jumper at J11 and install a two pin header. Leave the jumper J11 open.

This cuts the clock signal from the OpenSDA circuit to PTA0 (SWD_CLK/EZP_CLK) of the K64 processor.

DediProg Split Cable – Note Pin 3 – Orange is CS1 NOT MISO as shown in the picture

K64 Pinout for PT0 – PT4 lines which are used for EzPort with Reset Line

PTA0 (EZP_CLK) (pin 34 k64) is on pin 2 of J2 (2x10) - Gray Wire on DediProg Split Cable
PTA1 (EZP_DI) (pin 35 k64) is on pin 8 of J1 (2x8) Black Wire on DediProg Split Cable
PTA2 (EZP_DO) (pin 36 K64) is pin 12 j1 (2x8) and on pin 6 of SWD connector - GREEN Wire on DediProg Split Cable

Reset Line (pin 52 on K64) is on pin 6 of J3 (2x8) - red wire on DediProg Split Cable

Gnd are pins 12 and 14 on J3 (2x8) White on DediProg Split Cable

EZP_CS – which is also NMI line – PTA4 – connects to SW3

PTA4 (EZP_CS_B) (pin 38) is connected to SW3 - Orange Wire on DediProg Split Cable

Note: on rev D1 board/schematic – R75 is DNP (do not populate) – so should not be too hard for the SF600 programmer to pull PTA4 (EZ_CS) low with just a 0.1uF cap on the line. Pulling the EZP_CS line low is how the K64 is put into EzPort mode.

On the K64, the SWD/JTAG pins and EzPort pins are multiplexed on the processor. The state of the EZP_CS signal is sampled at reset to determine whether the SWD/JTAG pin functions or the EzPort pin functions are enabled on the pins. If EZP_CS is high at reset, then SWD/JTAG functions are enabled on the pins. If EZP_CS is low at reset, then EzPORT pin functions are enabled.

Note: I’ve installed a wire on pin 1 of SW3 that connects to the Orange Wire on Split Cable – CS1

All the other signals were accessible via the Arduino connectors.

Below is what final wiring looks like.

Its a bit of a rats nest, but I've verified all the connections so pretty sure its NOT a broken connection problem.

DediProg Engineer Software Set up

These are the directions for EzPort Set up document. I’ve followed them and tried various alternatives. No option seems able to detect the part type – nor read the part’s memory.

1.) Open DediProg Engineering software.
1. a. Click on Detect and select Freescale part number – Note: No K64 part number but K61, K60 and K70 part numbers

Do I pick K61FN1M0 or MK64FN1M0 or K70FN1MO – which all seem to have 1M of flash?

I picked MK61FN1MO - DediProg has indicated this is a valid choice.

“Config->Miscellaneous Setting->SPI Clock Setting” to select SPI clock frequency according to your application system frequency.

Really don’t have an SPI clock – but I’ll pick 12MHZ – Note: DediProg has indicated this choice is valid

3. Enable "Config->Batch Operations->Enable Freescale EzPort MCU & Send the DIV

value".

4. Set the flash machine clock (FCLK) by the following procedure:
A. If Fsys is greater than 25.6 MHz, PRDIV8 equals 1; otherwise, PRDIV8 equals 0.
B. Determine DIV[5:0] by using the following equation. Keep only the integer portion of the result and discard any fraction. Do not round the result.

For proper program and erase operations, it is critical to set FCLK between150 kHz

and 200 kHz. Array damage due to overstress can occur when FCLK is less than 150

kHz. Incomplete programming and erasure can occur when FCLK is greater than 200
kHz.

So lets try 22.5mhz (default internal clock of K64) / 400000 = 56 = 0x38 - DediProg did not confirm this value - I picked 22.5 mhz because I assumed the K64’s internal clock is running the part at reset before any code initializes the clock registers.

Question - What is the likely or default system clock rate of a K64 right after reset?

Enable DediProg Engineering software "Config->Batch Operations->Enable Freescale EzPort MCU & Send the DIV value" and fill out the DIV value.

5. Load file and then click on “Batch”, EzPort will be enabled and software will program the

Freescale MCU according to Batch options.

6. For Read command to return the correct data, the EzPort Clock (EZPCK) must run at no more than divide by eight of the internal system clock.

Results

When I hit detect button in software, DediProg does NOT detect part type. It seems to try to reset board, but it doesn’t seem to recognize K64 part.

When I manually input K61, K60 or K70 part, I still can’t read K64 memory.

10/13/2015

Installed new beta software – no change really

All attempts to identify the chip fail.

I’ve also tried the edit button (read the chip) but they also fail.