topic External SRAM and Flexbus - Help Needed in Kinetis Microcontrollers

External SRAM and Flexbus - Help Needed

weblar — Thu, 30 Jul 2015 15:09:25 GMT

Hi,

I've hooked up an external SRAM chip to the Flexbus of a Kinetis K66.

Having written a very basic application to test that the SRAM is working ok, I've since run into problems and I think it may be related to the wiring of my Flexbus signals through to the SRAM. Just for reference, I'm using a IS61WV102416BLL chip.

My Flexbus to SRAM pin mapping is as follows:

FB_AD[15:0] = SRAM_A[15:0]

FB_A[19:16] = SRAM_A[19:16]

FB_AD[31:16] = SRAM_D[15:0]

FB_CS0 = SRAM_CE

FB_OE = SRAM_OE

FB_RW = SRAM_WE

FB_LB = SRAM_LB

FB_HB = SRAM_HB

I'm using the following code to initialize the FB:

#define ADDR 0x90000000

// Address signals [19:0]

PORTD_PCR6 = PORT_PCR_MUX(5); // FB.AD0

PORTD_PCR5 = PORT_PCR_MUX(5); // FB.AD1

PORTD_PCR4 = PORT_PCR_MUX(5); // FB.AD2

PORTD_PCR3 = PORT_PCR_MUX(5); // FB.AD3

PORTD_PCR2 = PORT_PCR_MUX(5); // FB.AD4

PORTC_PCR10 = PORT_PCR_MUX(5); // FB.AD5

PORTC_PCR9 = PORT_PCR_MUX(5); // FB.AD6

PORTC_PCR8 = PORT_PCR_MUX(5); // FB.AD7

PORTC_PCR7 = PORT_PCR_MUX(5); // FB.AD8

PORTC_PCR6 = PORT_PCR_MUX(5); // FB.AD9

PORTC_PCR5 = PORT_PCR_MUX(5); // FB.AD10

PORTC_PCR4 = PORT_PCR_MUX(5); // FB.AD11

PORTC_PCR2 = PORT_PCR_MUX(5); // FB.AD12

PORTC_PCR1 = PORT_PCR_MUX(5); // FB.AD13

PORTC_PCR0 = PORT_PCR_MUX(5); // FB.AD14

PORTB_PCR18 = PORT_PCR_MUX(5); // FB.AD15

PORTD_PCR8 = PORT_PCR_MUX(5); // FB.A16

PORTD_PCR9 = PORT_PCR_MUX(5); // FB.A17

PORTD_PCR10 = PORT_PCR_MUX(5); // FB.A18

PORTD_PCR11 = PORT_PCR_MUX(5); // FB.A19

// Data signals [15:0]

PORTB_PCR17 = PORT_PCR_MUX(5); // FB.D0 [FB.AD16]

PORTB_PCR16 = PORT_PCR_MUX(5); // FB.D1 [FB.AD17]

PORTB_PCR11 = PORT_PCR_MUX(5); // FB.D2 [FB.AD18]

PORTB_PCR10 = PORT_PCR_MUX(5); // FB.D3 [FB.AD19]

PORTB_PCR9 = PORT_PCR_MUX(5); // FB.D4 [FB.AD20]

PORTB_PCR8 = PORT_PCR_MUX(5); // FB.D5 [FB.AD21]

PORTB_PCR7 = PORT_PCR_MUX(5); // FB.D6 [FB.AD22]

PORTB_PCR6 = PORT_PCR_MUX(5); // FB.D7 [FB.AD23]

PORTC_PCR15 = PORT_PCR_MUX(5); // FB.D8 [FB.AD24]

PORTC_PCR14 = PORT_PCR_MUX(5); // FB.D9 [FB.AD25]

PORTC_PCR13 = PORT_PCR_MUX(5); // FB.D10 [FB.AD26]

PORTC_PCR12 = PORT_PCR_MUX(5); // FB.D11 [FB.AD27]

PORTB_PCR23 = PORT_PCR_MUX(5); // FB.D12 [FB.AD28]

PORTB_PCR22 = PORT_PCR_MUX(5); // FB.D13 [FB.AD29]

PORTB_PCR21 = PORT_PCR_MUX(5); // FB.D14 [FB.AD30]

PORTB_PCR20 = PORT_PCR_MUX(5); // FB.D15 [FB.AD31]

// Byte control signals [HB:LB]

PORTC_PCR18 = PORT_PCR_MUX(5); // FB.BE15_8

PORTC_PCR17 = PORT_PCR_MUX(5); // FB.BE7_0

// Chip select signal

PORTD_PCR1 = PORT_PCR_MUX(5); // FB.CS0#

// Read/Write signal

PORTC_PCR11 = PORT_PCR_MUX(5); // FB.RW#

// Output enable signal

PORTB_PCR19 = PORT_PCR_MUX(5); // FB.OE#

SIM_SOPT2 |= SIM_SOPT2_FBSL(3);

SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;

FB_CSAR0 = ADDR;

// 16bit data port size

// Auto-acknowledge

// Some wait states

// Byte-enable mode so BE is asserted for read and write

FB_CSCR0 = FB_CSCR_PS(2) | FB_CSCR_AA_MASK | FB_CSCR_WS(5) | FB_CSCR_BEM_MASK;

FB_CSMR0 = FB_CSMR_V_MASK | FB_CSMR_BAM(0x7);

// Enable FB_BE_15_8 and FB_BE_7_0

FB_CSPMCR = FB_CSPMCR_GROUP4(2) | FB_CSPMCR_GROUP5(2);

With the following code used to write/read back data from the SRAM:

*((uint8_t *)ADDR + 1) = 0x05;

*((uint8_t *)ADDR + 2) = 0x04;

*((uint8_t *)ADDR + 3) = 0x03;

*((uint8_t *)ADDR + 4) = 0x02;

*((uint8_t *)ADDR + 5) = 0x01;

f = *((uint8_t *)ADDR + 1);

printf("%x", f);

f = *((uint8_t *)ADDR + 2);

printf("%x", f);

f = *((uint8_t *)ADDR + 3);

printf("%x", f);

f = *((uint8_t *)ADDR + 4);

printf("%x", f);

f = *((uint8_t *)ADDR + 5);

printf("%x", f);

The result of printf either comes out as a "90" or a "00" which is coincidental, based on the ADDR value.

I'm not convinced the wiring of the Flexbus is entirely correct but equally, I'm sure I'm missing something in the initialization.

Any advice would be greatly appreciated.

Kev

Re: External SRAM and Flexbus - Help Needed

DavidS — Thu, 30 Jul 2015 17:40:24 GMT

Hi Kev,

Please review following link to see if it helps.

Flexbus in MQX

Regards,

David

Re: External SRAM and Flexbus - Help Needed

weblar — Fri, 31 Jul 2015 07:28:42 GMT

Hi David,

Thanks for the link.

Unfortunately, the scope of the document isn't sufficient for me to see whether my Flexbus is set up correctly. I've used the Flexbus on an LCD display before and had no issue - it works perfectly - I just can't decide whether its a hardware issue on my board due to the signals being mapped incorrectly (the upper address bits) or a software initialization/configuration issue.

Kind regards,

Kevin

Re: External SRAM and Flexbus - Help Needed

weblar — Fri, 31 Jul 2015 09:01:15 GMT

Ok, so I guess a couple of things I've noticed following this post:

https://community.freescale.com/thread/309447

My pin mux-ing for the upper 4 address signals was incorrect - I specified PORT_PCR_MUX(5) but it should have been PORT_PCR_MUX(6). Also, it would appear that because my data is not byte-lane shifted (BLS = 0) and resides on FB_AD[31:16] that I should be using BE_31_24 and BE_23_16 rather than BE_15_8 and BE_7_0.

I've changed the former, which made no difference. I'm hoping that the latter will do it!

Can anyone offer any advice on the above?

Kind regards,

Kevin

UPDATE

I'm now more confused. The SRAM_HB and SRAM_LB signals are routed through to PORTC_18 and PORTC_19 respectively. In the reference manual, these signals (for pin mux 5) are descried as FB_BE15_8_BLS23_16_b and FB_BE7_0_BLS31_24_b. Does this now mean that I am actually using the correct ones??

Re: External SRAM and Flexbus - Help Needed

weblar — Mon, 03 Aug 2015 10:45:42 GMT

Ok, so having a weekend off has clearly helped - the SRAM access now works as expected.

The only thing I needed to change from my initial setup was to swap the HB/LB signals from PORTC[18] and [19] to PORTC[17] and [18] respectively, due to the fact that BLS=0.

This post proved most useful:

https://community.freescale.com/message/322857

Re: External SRAM and Flexbus - Help Needed

michaelhuslig — Tue, 04 Aug 2015 20:04:07 GMT

Please see External SRAM and non-multiplexed Flexbus