Kinetis MicrocontrollersのトピックRe: Master SPI signal is incorrect

Master SPI signal is incorrect

willx — Wed, 03 Dec 2014 23:14:12 GMT

I have a FRDM-KL03 and a FRDM-K64 and I tried running both as SPI master and I'm seeing the same behavior on both. The CLK line looks weird. See attachments. Good screenshot is when host adapter is acting as master and bad screenshot is when KL03 or K64 is acting as master.

Config on KL03 looks as follows:

C1 has SPIE, SPE, CPOL, MSTR and SSOE bits set.

C2 has SPISWAI and MODFEN bits set.

BR = 0x0;

The error says: "The initial (idle) state of the CLK line does not match the settings".

Any help is appreciated.

Re: Master SPI signal is incorrect

mjbcswitzerland — Thu, 04 Dec 2014 11:56:47 GMT

I would suggest that you have the SPI speed set too high for your logic analyser (only 10MHz) to be able to sample correctly.

Set a lower SPI speed and then it will probably look similar (if the SW is correct).

Regards

Mark

Re: Master SPI signal is incorrect

adriancano — Thu, 04 Dec 2014 20:42:54 GMT

Hi,

"The initial (idle) state of the CLK line does not match the settings" this means that the the protocol settings in the analyzer software are not correct. If you are configuring CPOL = 1 then your are selecting Active-low SPI clock (idles high) please check that the Analyzer settings for the SPI protocol are set to "Clock is high when Inactive CPOL = 1 "

Hope this information can help you.

Best Regards,
Adrian Sanchez Cano
Technical Support Engineer
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Re: Master SPI signal is incorrect

willx — Thu, 04 Dec 2014 22:20:07 GMT

Thanks Mark.

This helped on the KL03, but not on the K64. I can now see the expected signals on the KL03.

Re: Master SPI signal is incorrect

willx — Thu, 04 Dec 2014 22:26:19 GMT

Thanks Adrian.

The setting on the logic analyzer ("Clock is high when Inactive CPOL = 1") matches the one programmed on the K64 SPI (CPOL bit is set) and now I'm able to see correct clock signal and MOSI but the SS line is not asserted (see No_SS.png attachment below).

Actually, it is asserted just for a little bit. See SS_blip.png below which is a zoomed section from where the red dot is in No_SS.png.

Any ideas on what could be the problem here?

Re: Master SPI signal is incorrect

mjbcswitzerland — Thu, 04 Dec 2014 22:37:05 GMT

Check the SPI driver(s) being used - the K64 has automatic CS control controlled by its FIFO control words.

The KL03 only works in automatic SS output when set up with SSOE in SPIx_C1 and MODFEN is set to 0 in SPIx_C2.

Regards

Mark

Re: Master SPI signal is incorrect

adriancano — Thu, 04 Dec 2014 22:50:13 GMT

Hi,

What are your SPI configurations specially for the bits that control the SS behavior like the:

SPIx_MCR[PCSSE] that for a standard comunication the value is 0: PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.

SPIx_MCR[PCSIS] to determinate the inactive state of the SS signal.

Also if you slave allow the Continuous mode I recommend to set the SPIx_PUSHR[CONT] signal to Keep PCSn signals asserted between transfers. You can check more information about the CONT bit in the K64 Reference Manual in the section 50.4.4.3 Continuous Selection Format.

I had some problems in the past using the Analyzer without the GND probes, I recommend to connect the GND probes to your hardware.

Hope this information can help you.

Re: Master SPI signal is incorrect

willx — Thu, 04 Dec 2014 23:53:44 GMT

I checked the config:

SPIx_MCR[PCSSE] is 0

SPIx_MCR[PCSIS] is all 1's

GND pins are connected too.

The slave is a KL03 which I don't think supports continuous mode.

Re: Master SPI signal is incorrect

willx — Fri, 05 Dec 2014 18:35:28 GMT

This is what I'm configuring in setting up the K64 as master. Please let me know if you find something unexpected. Appreciate your help.

// Enable the clocks for Ports C and D and SPI0

SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;

SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK;

SIM_SCGC6 |= SIM_SCGC6_SPI0_MASK;

// Configure the ports to be used by SPI0

PORTC_PCR4 = PORT_PCR_MUX(2); // CS

PORTC_PCR5 = PORT_PCR_MUX(2); // SCLK

PORTD_PCR2 = PORT_PCR_MUX(2); // MOSI

PORTC_PCR7 = PORT_PCR_MUX(2); // MISO

// Enable SPI0 IRQ

int irq = GET_IRQ_NUM(INT_SPI0);

set_irq_priority(irq, 7);

enable_irq(irq);

// Configure SPI0 registers

SPI0_BR = X; // I tried multiple baud rate values but the output has the same form but different duration

// Disable and clear SPI

SPI0_MCR &= (~ SPI_MCR_MDIS_MASK);

SPI0_MCR = SPI_MCR_HALT_MASK | SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK;

SPI0_MCR |= SPI_MCR_MSTR_MASK;

SPI0_CTAR = SPI_CTAR_CPOL_MASK | SPI_CTAR_FMSZ(7) | ;

// Receive FIFO Overflow Overwrite Enable

SPI0_MCR |= SPI_MCR_ROOE_MASK;

// Set CS0-7 inactive high

SPI0_MCR |= SPI_MCR_PCSIS_MASK;

// Receive FIFO Overflow Request Enable

SPI0_RSER |= SPI_RSER_RFOF_RE_MASK;

// Clear all flags

SPI0_SR = 0xFFFFFFFF;

// Enable SPI

SPI0_MCR &= ~SPI_MCR_HALT_MASK;

Re: Master SPI signal is incorrect

willx — Fri, 05 Dec 2014 19:35:29 GMT

When I was transmitting before, I was using this:

SPI0_PUSHR = SPI_PUSHR_CONT_MASK | SPI_PUSHR_TXDATA(0x1f);

When I add SPI_PUSHR_PCS_MASK, I can see that the CS line stays low but there's as expected but I still see the red dot and the blip on MOSI line and get the error that says "The initial (idle) state of the CLK line does not match the settings".

Re: Master SPI signal is incorrect

mjbcswitzerland — Fri, 05 Dec 2014 20:04:34 GMT

There are various other settings in the SPIx_CTAR register which control the timing of the CS line in relation to the clock/data. I suggest you experiment with these until you understand their effects and you may find that the glitch is occurring due to such things not being co-ordinated correctly.

Regards

Mark

Re: Master SPI signal is incorrect

adriancano — Fri, 05 Dec 2014 21:03:27 GMT

Hi,

You can change the configuration of the Analyzer software changing the parameter on the settings to see which match the real signals from the device.

Regards,

Adrian