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    <title>topic Re: SPI and DMA CS does not disable in Kinetis Microcontrollers</title>
    <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-and-DMA-CS-does-not-disable/m-p/364063#M18655</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I apologize for the late response, I am not aware of an issue like this. But I have some points to check.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It is probably that your configuration has the continuous mode enable in the last transmission and this is causing the PCSx line remains low waiting for the next frame. Please check the status your are configuring for the PUSHR[CONT] bit in the last transfer.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also, you need to ensure that in the last transfer the PUSHR[EOQ] bit is set to indicate is the last one in the queue and the bus becomes free.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope this information can help you&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Adrian Sanchez Cano&lt;BR /&gt;Technical Support Engineer&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 16 Feb 2015 22:43:09 GMT</pubDate>
    <dc:creator>adriancano</dc:creator>
    <dc:date>2015-02-16T22:43:09Z</dc:date>
    <item>
      <title>SPI and DMA CS does not disable</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-and-DMA-CS-does-not-disable/m-p/364060#M18652</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Good morning..&lt;/P&gt;&lt;P&gt;I am testing on the FRDM-K64.&lt;/P&gt;&lt;P&gt;I have initialized the SPI and DMA to transfer. The transfer is looking ok on the scope with one problem.&lt;/P&gt;&lt;P&gt;The second CS signal remain in the enable status in the end of the transfer, I would like to see it disabled as the other.&lt;/P&gt;&lt;P&gt;Suggestions???&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Pietro&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Feb 2015 14:08:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-and-DMA-CS-does-not-disable/m-p/364060#M18652</guid>
      <dc:creator>pietrodicastri</dc:creator>
      <dc:date>2015-02-10T14:08:36Z</dc:date>
    </item>
    <item>
      <title>Re: SPI and DMA CS does not disable</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-and-DMA-CS-does-not-disable/m-p/364061#M18653</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I do not completely understand what do you mean with the second CS? Can you please be more specific?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You can refer to this document, it might be useful for your application:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-102981"&gt;Using the DMA module in Kinetis Devices&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Hope this information can help you&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Adrian Sanchez Cano&lt;BR /&gt;Technical Support Engineer&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Feb 2015 23:31:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-and-DMA-CS-does-not-disable/m-p/364061#M18653</guid>
      <dc:creator>adriancano</dc:creator>
      <dc:date>2015-02-10T23:31:11Z</dc:date>
    </item>
    <item>
      <title>Re: SPI and DMA CS does not disable</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-and-DMA-CS-does-not-disable/m-p/364062#M18654</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Adrian&lt;/P&gt;&lt;P&gt;Thank You for the assistance.&lt;/P&gt;&lt;P&gt;The signal I mean are the SPI0_PCS1 and SPI0_PCS0. &lt;/P&gt;&lt;P&gt;Everything is working with the surprise that the last transfer updates all of the PCSx signal as requested &lt;/P&gt;&lt;P&gt;only when the transfer begins, not when the transfer ends. The enabled PCSx in the last transfer remain enabled&lt;/P&gt;&lt;P&gt;when the transfer stops.&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;The trick is to add a dummy transfer with all of the PCSx signal disabled, but I don t like to do. I suppose a solution exists.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank You&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Feb 2015 07:50:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-and-DMA-CS-does-not-disable/m-p/364062#M18654</guid>
      <dc:creator>pietrodicastri</dc:creator>
      <dc:date>2015-02-11T07:50:24Z</dc:date>
    </item>
    <item>
      <title>Re: SPI and DMA CS does not disable</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-and-DMA-CS-does-not-disable/m-p/364063#M18655</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I apologize for the late response, I am not aware of an issue like this. But I have some points to check.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It is probably that your configuration has the continuous mode enable in the last transmission and this is causing the PCSx line remains low waiting for the next frame. Please check the status your are configuring for the PUSHR[CONT] bit in the last transfer.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also, you need to ensure that in the last transfer the PUSHR[EOQ] bit is set to indicate is the last one in the queue and the bus becomes free.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope this information can help you&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Adrian Sanchez Cano&lt;BR /&gt;Technical Support Engineer&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Feb 2015 22:43:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-and-DMA-CS-does-not-disable/m-p/364063#M18655</guid>
      <dc:creator>adriancano</dc:creator>
      <dc:date>2015-02-16T22:43:09Z</dc:date>
    </item>
    <item>
      <title>Re: SPI and DMA CS does not disable</title>
      <link>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-and-DMA-CS-does-not-disable/m-p/364064#M18656</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes...&lt;/P&gt;&lt;P&gt;That's it&lt;/P&gt;&lt;P&gt;Thank You&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 17 Feb 2015 08:52:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Microcontrollers/SPI-and-DMA-CS-does-not-disable/m-p/364064#M18656</guid>
      <dc:creator>pietrodicastri</dc:creator>
      <dc:date>2015-02-17T08:52:17Z</dc:date>
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