Help clearing SPI TX buffers

markosiponen — Fri, 15 Aug 2014 15:18:30 GMT

I'm using a MK10FN1M0VLQ12.

I have setup DMA to transfer data to SPI2_PUSHR.

I have not enabled TX FIFO or RX FIFO for the SPI.

I see that when I enable the DMA channel the DMA immediatly transfers 2 byte. Why is this happening. Why not only one byte? Is the SPI2_PUSHR double buffered?

And another problem. When SPI chip select goes high I need to reset the DMA and also any possible outgoing data in the SPI. How can I reset the SPI TX buffers?

What I mean is if SR[TFFF] is 0 (TX FIFO is full) how do i get it to become 1 (TX FIFO is not full)?

Update:

Now I have tested an approach here. I have found that the following works:

// Disable DMA MUX 0 channel first before we change anything

DMAMUX0->CHCFG[MAIN_SPI_TX_DMA_CH] = 0;

DMA0->CERQ = MAIN_SPI_TX_DMA_CH; // Disable DMA Request

// Halt SPI

SPI2->MCR |= SPI_MCR_HALT_MASK;

//Clear TX FIFO

SPI2->MCR |= SPI_MCR_CLR_TXF_MASK;

// Unhalt SPI

SPI2->MCR &= (uint32_t)~(uint32_t)(SPI_MCR_HALT_MASK);

Setup the DMA

...

// Enables DMA channel and select DMA MUX Request Sources for the DMA Channel

DMAMUX0->CHCFG[MAIN_SPI_TX_DMA_CH] = DMAMUX_CHCFG_SOURCE(21) | DMAMUX_CHCFG_ENBL_MASK; // 21 = SPI2 Transmit

I must halt the SPI2 and then clear the TX FIFO. Else it will not work.

Is this the correct way to do it?

Re: Help clearing SPI TX buffers

Hui_Ma — Tue, 19 Aug 2014 09:14:08 GMT

Hi,

I do a test with K60_100MHz DSPI module and check when write a byte to SPI_PUSHR register how many bytes the SPI will transfer. The result is only one.

Please refer below code to disable TX/RX FIFO and Clear TX/RX counter during SPI initialization.

And it need to set SPIx_CTARn register [FMSZ] bits value to 0x7 for a byte data transfer.

The test software source code is based on spi_demo from below link:

KINETIS512_V2_SC (Kinetis 100MHz Rev 2 Example Projects):

Kinetis K60 100 MHz MCU Tower System Module|Freescale

Wish it helps.
best regards
Ma Hui

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Help clearing SPI TX buffers

Re: Help clearing SPI TX buffers